bit8_portin.tan.qmsg

Source of Grabber Board

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Timing Analyzer " "Info: Running Quartus II Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 4.1 Build 181 06/29/2004 SJ Web Edition " "Info: Version 4.1 Build 181 06/29/2004 SJ Web Edition" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Sep 09 01:06:35 2006 " "Info: Processing started: Sat Sep 09 01:06:35 2006" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --import_settings_files=off --export_settings_files=off bit8_PortIn -c bit8_PortIn " "Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off bit8_PortIn -c bit8_PortIn" {  } {  } 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "CLK_H1 " "Info: Assuming node CLK_H1 is an undefined clock" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 56 56 224 72 "CLK_H1" "" } { 328 96 168 344 "CLK_H1" "" } } } } { "c:/program files/altera/quartus41/bin/Assignment Editor.qase" "" "" { Assignment "c:/program files/altera/quartus41/bin/Assignment Editor.qase" 1 { { 0 "CLK_H1" } } } }  } 0}  } {  } 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "CLK_H1 " "Info: No valid register-to-register paths exist for clock CLK_H1" {  } {  } 0}
{ "Info" "ITDB_TSU_RESULT" "inst43\[0\] IN\[0\] CLK_H1 4.000 ns register " "Info: tsu for register inst43\[0\] (data pin = IN\[0\], clock pin = CLK_H1) is 4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.600 ns + Longest pin register " "Info: + Longest pin to register delay is 6.600 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.100 ns) 3.100 ns IN\[0\] 1 PIN PIN_64 1 " "Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_64; Fanout = 1; PIN Node = 'IN\[0\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { IN[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 160 56 224 176 "IN\[7..0\]" "" } { 296 96 168 312 "IN\[7..0\]" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.600 ns) + CELL(0.900 ns) 6.600 ns inst43\[0\] 2 REG LC4_B11 1 " "Info: 2: + IC(2.600 ns) + CELL(0.900 ns) = 6.600 ns; Loc. = LC4_B11; Fanout = 1; REG Node = 'inst43\[0\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.500 ns" { IN[0] inst43[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.000 ns 60.61 % " "Info: Total cell delay = 4.000 ns ( 60.61 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.600 ns 39.39 % " "Info: Total interconnect delay = 2.600 ns ( 39.39 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "6.600 ns" { IN[0] inst43[0] } "NODE_NAME" } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "1.300 ns + " "Info: + Micro setup delay of destination is 1.300 ns" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CLK_H1 destination 3.900 ns - Shortest register " "Info: - Shortest clock path from clock CLK_H1 to destination register is 3.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.900 ns) 1.900 ns CLK_H1 1 CLK PIN_43 8 " "Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "" { CLK_H1 } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 56 56 224 72 "CLK_H1" "" } { 328 96 168 344 "CLK_H1" "" } } } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(0.000 ns) 3.900 ns inst43\[0\] 2 REG LC4_B11 1 " "Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_B11; Fanout = 1; REG Node = 'inst43\[0\]'" {  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "2.000 ns" { CLK_H1 inst43[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" "" "" { Schematic "d:/uav/hw/fpga/uavfpga/bit8_portin/bit8_PortIn.bdf" { { 288 304 368 368 "inst43" "" } } } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.900 ns 48.72 % " "Info: Total cell delay = 1.900 ns ( 48.72 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 51.28 % " "Info: Total interconnect delay = 2.000 ns ( 51.28 % )" {  } {  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[0] } "NODE_NAME" } } }  } 0}  } { { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "6.600 ns" { IN[0] inst43[0] } "NODE_NAME" } } } { "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" "" "" { Report "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn_cmp.qrpt" Compiler "bit8_PortIn" "UNKNOWN" "V1" "d:/uav/hw/fpga/uavfpga/bit8_portin/db/bit8_PortIn.quartus_db" { Floorplan "" "" "3.900 ns" { CLK_H1 inst43[0] } "NODE_NAME" } } }  } 0}