bit8_portin.tan.rpt

Source of Grabber Board

; N/A   ; None              ; 14.200 ns       ; DSP_nCS ; D[3] ;
; N/A   ; None              ; 14.200 ns       ; DSP_nCS ; D[6] ;
; N/A   ; None              ; 14.100 ns       ; DSP_nCS ; D[7] ;
; N/A   ; None              ; 14.000 ns       ; DSP_nCS ; D[1] ;
; N/A   ; None              ; 14.000 ns       ; DSP_nCS ; D[2] ;
+-------+-------------------+-----------------+---------+------+


+------------------------------------------------------------------------+
; th                                                                     ;
+---------------+-------------+-----------+-------+-----------+----------+
; Minimum Slack ; Required th ; Actual th ; From  ; To        ; To Clock ;
+---------------+-------------+-----------+-------+-----------+----------+
; N/A           ; None        ; 1.000 ns  ; IN[6] ; inst43[6] ; CLK_H1   ;
; N/A           ; None        ; 0.900 ns  ; IN[5] ; inst43[5] ; CLK_H1   ;
; N/A           ; None        ; 0.800 ns  ; IN[7] ; inst43[7] ; CLK_H1   ;
; N/A           ; None        ; -1.100 ns ; IN[2] ; inst43[2] ; CLK_H1   ;
; N/A           ; None        ; -1.100 ns ; IN[4] ; inst43[4] ; CLK_H1   ;
; N/A           ; None        ; -1.300 ns ; IN[0] ; inst43[0] ; CLK_H1   ;
; N/A           ; None        ; -1.300 ns ; IN[1] ; inst43[1] ; CLK_H1   ;
; N/A           ; None        ; -1.300 ns ; IN[3] ; inst43[3] ; CLK_H1   ;
+---------------+-------------+-----------+-------+-----------+----------+


+-----------------------------------------------------------------------------------+
; Minimum tco                                                                       ;
+---------------+------------------+----------------+-----------+------+------------+
; Minimum Slack ; Required Min tco ; Actual Min tco ; From      ; To   ; From Clock ;
+---------------+------------------+----------------+-----------+------+------------+
; N/A           ; None             ; 9.900 ns       ; inst43[6] ; D[6] ; CLK_H1     ;
; N/A           ; None             ; 9.900 ns       ; inst43[4] ; D[4] ; CLK_H1     ;
; N/A           ; None             ; 9.900 ns       ; inst43[2] ; D[2] ; CLK_H1     ;
; N/A           ; None             ; 10.000 ns      ; inst43[3] ; D[3] ; CLK_H1     ;
; N/A           ; None             ; 10.000 ns      ; inst43[0] ; D[0] ; CLK_H1     ;
; N/A           ; None             ; 10.900 ns      ; inst43[7] ; D[7] ; CLK_H1     ;
; N/A           ; None             ; 10.900 ns      ; inst43[5] ; D[5] ; CLK_H1     ;
; N/A           ; None             ; 10.900 ns      ; inst43[1] ; D[1] ; CLK_H1     ;
+---------------+------------------+----------------+-----------+------+------------+


+----------------------------------------------------------------------+
; Minimum tpd                                                          ;
+---------------+-------------------+-----------------+---------+------+
; Minimum Slack ; Required P2P Time ; Actual P2P Time ; From    ; To   ;
+---------------+-------------------+-----------------+---------+------+
; N/A           ; None              ; 14.000 ns       ; DSP_nCS ; D[2] ;
; N/A           ; None              ; 14.000 ns       ; DSP_nCS ; D[1] ;
; N/A           ; None              ; 14.100 ns       ; DSP_nCS ; D[7] ;
; N/A           ; None              ; 14.200 ns       ; DSP_nCS ; D[6] ;
; N/A           ; None              ; 14.200 ns       ; DSP_nCS ; D[3] ;
; N/A           ; None              ; 14.200 ns       ; DSP_nCS ; D[0] ;
; N/A           ; None              ; 14.300 ns       ; DSP_nCS ; D[5] ;
; N/A           ; None              ; 14.300 ns       ; DSP_nCS ; D[4] ;
; N/A           ; None              ; 14.500 ns       ; -IORD   ; D[2] ;
; N/A           ; None              ; 14.500 ns       ; -IORD   ; D[1] ;
; N/A           ; None              ; 14.600 ns       ; -IORD   ; D[7] ;
; N/A           ; None              ; 14.700 ns       ; -IORD   ; D[6] ;
; N/A           ; None              ; 14.700 ns       ; -IORD   ; D[3] ;
; N/A           ; None              ; 14.700 ns       ; -IORD   ; D[0] ;
; N/A           ; None              ; 14.800 ns       ; -IORD   ; D[5] ;
; N/A           ; None              ; 14.800 ns       ; -IORD   ; D[4] ;
+---------------+-------------------+-----------------+---------+------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 4.1 Build 181 06/29/2004 SJ Web Edition
    Info: Processing started: Sat Sep 09 01:06:35 2006
Info: Command: quartus_tan --import_settings_files=off --export_settings_files=off bit8_PortIn -c bit8_PortIn
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node CLK_H1 is an undefined clock
Info: No valid register-to-register paths exist for clock CLK_H1
Info: tsu for register inst43[0] (data pin = IN[0], clock pin = CLK_H1) is 4.000 ns
    Info: + Longest pin to register delay is 6.600 ns
        Info: 1: + IC(0.000 ns) + CELL(3.100 ns) = 3.100 ns; Loc. = PIN_64; Fanout = 1; PIN Node = 'IN[0]'
        Info: 2: + IC(2.600 ns) + CELL(0.900 ns) = 6.600 ns; Loc. = LC4_B11; Fanout = 1; REG Node = 'inst43[0]'
        Info: Total cell delay = 4.000 ns ( 60.61 % )
        Info: Total interconnect delay = 2.600 ns ( 39.39 % )
    Info: + Micro setup delay of destination is 1.300 ns
    Info: - Shortest clock path from clock CLK_H1 to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC4_B11; Fanout = 1; REG Node = 'inst43[0]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
Info: tco from clock CLK_H1 to destination pin D[1] through register inst43[1] is 10.900 ns
    Info: + Longest clock path from clock CLK_H1 to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'inst43[1]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Longest register to pin delay is 6.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC8_A16; Fanout = 1; REG Node = 'inst43[1]'
        Info: 2: + IC(2.200 ns) + CELL(3.900 ns) = 6.100 ns; Loc. = PIN_70; Fanout = 0; PIN Node = 'D[1]'
        Info: Total cell delay = 3.900 ns ( 63.93 % )
        Info: Total interconnect delay = 2.200 ns ( 36.07 % )
Info: Longest tpd from source pin -IORD to destination pin D[4] is 14.800 ns
    Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_84; Fanout = 1; PIN Node = '-IORD'
    Info: 2: + IC(1.600 ns) + CELL(1.900 ns) = 5.400 ns; Loc. = LC1_C11; Fanout = 8; COMB Node = 'inst1'
    Info: 3: + IC(4.400 ns) + CELL(5.000 ns) = 14.800 ns; Loc. = PIN_59; Fanout = 0; PIN Node = 'D[4]'
    Info: Total cell delay = 8.800 ns ( 59.46 % )
    Info: Total interconnect delay = 6.000 ns ( 40.54 % )
Info: th for register inst43[6] (data pin = IN[6], clock pin = CLK_H1) is 1.000 ns
    Info: + Longest clock path from clock CLK_H1 to destination register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43[6]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro hold delay of destination is 1.400 ns
    Info: - Shortest pin to register delay is 4.300 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_42; Fanout = 1; PIN Node = 'IN[6]'
        Info: 2: + IC(1.500 ns) + CELL(0.900 ns) = 4.300 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43[6]'
        Info: Total cell delay = 2.800 ns ( 65.12 % )
        Info: Total interconnect delay = 1.500 ns ( 34.88 % )
Info: Minimum tco from clock CLK_H1 to destination pin D[6] through register inst43[6] is 9.900 ns
    Info: + Shortest clock path from clock CLK_H1 to source register is 3.900 ns
        Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_43; Fanout = 8; CLK Node = 'CLK_H1'
        Info: 2: + IC(2.000 ns) + CELL(0.000 ns) = 3.900 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43[6]'
        Info: Total cell delay = 1.900 ns ( 48.72 % )
        Info: Total interconnect delay = 2.000 ns ( 51.28 % )
    Info: + Micro clock to output delay of source is 0.900 ns
    Info: + Shortest register to pin delay is 5.100 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_B24; Fanout = 1; REG Node = 'inst43[6]'
        Info: 2: + IC(1.200 ns) + CELL(3.900 ns) = 5.100 ns; Loc. = PIN_67; Fanout = 0; PIN Node = 'D[6]'
        Info: Total cell delay = 3.900 ns ( 76.47 % )
        Info: Total interconnect delay = 1.200 ns ( 23.53 % )
Info: Shortest tpd from source pin DSP_nCS to destination pin D[2] is 14.000 ns
    Info: 1: + IC(0.000 ns) + CELL(1.900 ns) = 1.900 ns; Loc. = PIN_2; Fanout = 1; PIN Node = 'DSP_nCS'
    Info: 2: + IC(1.600 ns) + CELL(1.400 ns) = 4.900 ns; Loc. = LC1_C11; Fanout = 8; COMB Node = 'inst1'
    Info: 3: + IC(4.100 ns) + CELL(5.000 ns) = 14.000 ns; Loc. = PIN_71; Fanout = 0; PIN Node = 'D[2]'
    Info: Total cell delay = 8.300 ns ( 59.29 % )
    Info: Total interconnect delay = 5.700 ns ( 40.71 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Sat Sep 09 01:06:36 2006
    Info: Elapsed time: 00:00:00