addr_part.vhd

Source of Grabber Board

library ieee;
use ieee.std_logic_1164.all;

entity addr_part is
  port(
	LLC2, SEC : In std_logic;
	HREF, VREF : IN std_logic;
	DSP_ADDR : in std_logic_vector(18 downto 0);
	RAM_ADDR : OUT std_logic_vector(18 downto 0)
	);
end addr_part;

architecture honey of addr_part is
  signal TEMP_ADDR : std_logic_vector(18 downto 0);

  COMPONENT count19 port(SEC, LLC2, HREF_I : IN std_logic;
	RESET : IN std_logic;
	ADDRESS: BUFFER std_logic_vector(18 downto 0)
	); 
  end COMPONENT;

  COMPONENT addr_sec port(SEC_ADDR : IN std_logic;
	GRAB_ADDR_I,DSP_ADDR_I : IN std_logic_vector (18 downto 0);
	RAM_ADDR_I : OUT std_logic_vector (18 downto 0));
  end component;
begin
	U1 : count19 port map(SEC, LLC2, HREF, VREF, TEMP_ADDR);
	U2 : addr_sec port map(SEC, TEMP_ADDR, DSP_ADDR, RAM_ADDR);
end honey;