addr_sec.vhd.bak

Source of Grabber Board

library ieee;
use ieee.std_logic_1164.all;

entity addr_sec is
  port(
	SEC_ADDR : IN std_logic;
	GRAB_ADDR_I, DSP_ADDR_I : IN std_logic_vector(18 downto 0);
	RAM_ADDR_I : OUT std_logic_vector(18 downto 0)
	);
end addr_sec;

architecture honey of addr_sec is
begin
	RAM_ADDR_I <= GRAB_ADDR_I when SEC_ADDR = '1' else DSP_ADDR_I;	
end honey;