📄 graber.map.rpt
字号:
; Combinational cells for routing ; 0 ;
; Total registers ; 62 ;
; Total logic cells in carry chains ; 19 ;
; I/O pins ; 84 ;
; Maximum fan-out node ; A0_PWM1 ;
; Maximum fan-out ; 22 ;
; Total fan-out ; 340 ;
; Average fan-out ; 1.86 ;
+-----------------------------------+---------+
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------+
; |graber ; 99 (0) ; 62 ; 0 ; 84 ; 37 (0) ; 16 (0) ; 46 (0) ; 19 (0) ; 0 (0) ; |graber ;
; |74157:inst11| ; 3 (3) ; 0 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |graber|74157:inst11 ;
; |CLOCK:inst45| ; 41 (1) ; 27 ; 0 ; 0 ; 14 (1) ; 0 (0) ; 27 (0) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45 ;
; |freqdiv:inst16| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst16 ;
; |freqdiv:inst19| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst19 ;
; |freqdiv:inst1| ; 4 (4) ; 3 ; 0 ; 0 ; 1 (1) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst1 ;
; |freqdiv:inst20| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst20 ;
; |freqdiv:inst3| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst3 ;
; |freqdiv:inst6| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst6 ;
; |freqdiv:inst7| ; 6 (6) ; 4 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |graber|CLOCK:inst45|freqdiv:inst7 ;
; |addr_part:inst8| ; 38 (0) ; 19 ; 0 ; 0 ; 19 (0) ; 0 (0) ; 19 (0) ; 19 (0) ; 0 (0) ; |graber|addr_part:inst8 ;
; |addr_sec:U2| ; 19 (19) ; 0 ; 0 ; 0 ; 19 (19) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |graber|addr_part:inst8|addr_sec:U2 ;
; |count19:U1| ; 19 (0) ; 19 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 19 (0) ; 19 (0) ; 0 (0) ; |graber|addr_part:inst8|count19:U1 ;
; |lpm_counter:ADDRESS_rtl_0| ; 19 (0) ; 19 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 19 (0) ; 19 (0) ; 0 (0) ; |graber|addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0 ;
; |alt_counter_f10ke:wysi_counter| ; 19 (19) ; 19 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 19 (19) ; 19 (19) ; 0 (0) ; |graber|addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter ;
; |bit8_PortIn:inst4| ; 8 (8) ; 8 ; 0 ; 0 ; 0 (0) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |graber|bit8_PortIn:inst4 ;
; |bit8_PortIn:inst5| ; 9 (9) ; 8 ; 0 ; 0 ; 1 (1) ; 8 (8) ; 0 (0) ; 0 (0) ; 0 (0) ; |graber|bit8_PortIn:inst5 ;
+----------------------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 62 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 22 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 39 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------------------------+
; Parameter Settings for Inferred Entity Instance: addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0 ;
+------------------------+-------------------+----------------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+-------------------+----------------------------------------------------------+
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
; LPM_WIDTH ; 19 ; Untyped ;
; LPM_DIRECTION ; UP ; Untyped ;
; LPM_MODULUS ; 0 ; Untyped ;
; LPM_AVALUE ; UNUSED ; Untyped ;
; LPM_SVALUE ; UNUSED ; Untyped ;
; LPM_PORT_UPDOWN ; PORT_CONNECTIVITY ; Untyped ;
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; CARRY_CHAIN ; MANUAL ; Untyped ;
; CARRY_CHAIN_LENGTH ; 48 ; CARRY_CHAIN_LENGTH ;
; NOT_GATE_PUSH_BACK ; ON ; NOT_GATE_PUSH_BACK ;
; CARRY_CNT_EN ; SMART ; Untyped ;
; LABWIDE_SCLR ; ON ; Untyped ;
; USE_NEW_VERSION ; TRUE ; Untyped ;
; CBXI_PARAMETER ; NOTHING ; Untyped ;
+------------------------+-------------------+----------------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 6.0 Build 178 04/27/2006 SJ Web Edition
Info: Processing started: Wed Feb 25 19:02:00 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off graber -c graber
Info: Found 1 design units, including 1 entities, in source file graber.bdf
Info: Found entity 1: graber
Info: Found 1 design units, including 1 entities, in source file graberfinal.bdf
Info: Found entity 1: graberfinal
Info: Elaborating entity "graber" for the top level hierarchy
Warning: Pin "WE_" not connected
Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/others/maxplus2/74157.bdf
Info: Found entity 1: 74157
Info: Elaborating entity "74157" for hierarchy "74157:inst11"
Info: Elaborated megafunction instantiation "74157:inst11"
Warning: Using design file CLOCK.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: CLOCK
Info: Elaborating entity "CLOCK" for hierarchy "CLOCK:inst45"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/others/maxplus2/freqdiv.bdf
Info: Found entity 1: freqdiv
Info: Elaborating entity "freqdiv" for hierarchy "CLOCK:inst45|freqdiv:inst7"
Info: Elaborated megafunction instantiation "CLOCK:inst45|freqdiv:inst7"
Warning: Using design file bit8_PortIn.bdf, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
Info: Found entity 1: bit8_PortIn
Info: Elaborating entity "bit8_PortIn" for hierarchy "bit8_PortIn:inst5"
Warning: Using design file addr_part.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: addr_part-honey
Info: Found entity 1: addr_part
Info: Elaborating entity "addr_part" for hierarchy "addr_part:inst8"
Warning: Using design file count19.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: count19-honey
Info: Found entity 1: count19
Info: Elaborating entity "count19" for hierarchy "addr_part:inst8|count19:U1"
Warning: Using design file addr_sec.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
Info: Found design unit 1: addr_sec-honey
Info: Found entity 1: addr_sec
Info: Elaborating entity "addr_sec" for hierarchy "addr_part:inst8|addr_sec:U2"
Info: Inferred 1 megafunctions from design logic
Info: Inferred lpm_counter megafunction (LPM_WIDTH=19) from the following logic: "addr_part:inst8|count19:U1|ADDRESS[0]~0"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/megafunctions/lpm_counter.tdf
Info: Found entity 1: lpm_counter
Info: Elaborated megafunction instantiation "addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0"
Info: Found 1 design units, including 1 entities, in source file ../../../../../../../../altera/quartus60/libraries/megafunctions/alt_counter_f10ke.tdf
Info: Found entity 1: alt_counter_f10ke
Info: Elaborated megafunction instantiation "addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0|alt_counter_f10ke:wysi_counter", which is child of megafunction instantiation "addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0"
Info: Instantiated megafunction "addr_part:inst8|count19:U1|lpm_counter:ADDRESS_rtl_0" with the following parameter:
Info: Parameter "LPM_WIDTH" = "19"
Info: Parameter "LPM_DIRECTION" = "UP"
Info: Parameter "LPM_TYPE" = "LPM_COUNTER"
Warning: Design contains 1 input pin(s) that do not drive logic
Warning: No output dependent on input pin "WE_"
Info: Implemented 183 device resources after synthesis - the final resource count might be different
Info: Implemented 44 input pins
Info: Implemented 40 output pins
Info: Implemented 99 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 8 warnings
Info: Processing ended: Wed Feb 25 19:02:07 2009
Info: Elapsed time: 00:00:08
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -