virtexiipmgtboardinterface.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

 `endif

   SynchDCMLocked synch_pwm_locked_pwm
      (
       .locked_out(PWMSynchLocked), .locked_in(pwm_locked_out),
       .clock_in(pwm_clock_out)
       );

   SynchDCMLocked synch_pwm_locked_mgt
      (
       .locked_out(MGTSynchLocked), .locked_in(mgt_locked_out),
       .clock_in(mgt_clock_out)
       );

   SynchDCMLocked synch_pwm_locked_mgt_bot
      (
       .locked_out(MGTSynchLocked_bot), .locked_in(mgt_locked_out),
       .clock_in(mgt_clock_out_bot)
       );
              
   assign pwm_reset_out = ~PWMSynchLocked;
   assign mgt_reset_out = ~MGTSynchLocked;
   assign mgt_reset_out_bot = ~MGTSynchLocked_bot;

endmodule

module HumanInterface (LEDs_in, LEDs_out,
                       DIPs_in, DIPs_out,
                       push_buttons_in, push_buttons_out,
                       human_update_out,
                       clock_in, reset_in
                       );

   output [15:00] LEDs_out;
   output [35:00] DIPs_out;
   output [03:00] push_buttons_out;
   output         human_update_out;

   input [15:00]  LEDs_in;
   input [35:00]  DIPs_in;
   input [03:00]  push_buttons_in;
   input          clock_in, reset_in;

   //
   // Frame Rate Generation:
   SlowEnableGen enabler
      (
       .frame_enable_out(FrameEnable),
       .chase_enable_out(ChaseEnable),
       .reset_in(reset_in), .clock_in(clock_in)
       );

   LEDBank trick_leds0
      (
       .signals_in(LEDs_in[07:00]), .frame_enable_in(FrameEnable),
       .chase_enable_in(ChaseEnable), .LEDs_out(LEDs_out[07:00]),
       .clock_in(clock_in), .reset_in(reset_in)
       );

   LEDBank trick_leds1
      (
       .signals_in(LEDs_in[15:08]), .frame_enable_in(FrameEnable),
       .chase_enable_in(ChaseEnable), .LEDs_out(LEDs_out[15:08]),
       .clock_in(clock_in), .reset_in(reset_in)
       );

   SwitchDebounce switches
      (
       .switch_out({DIPs_out, push_buttons_out}),
       .switch_in({DIPs_in, push_buttons_in}),
       .update_out(human_update_out),
       .frame_enable_in(ChaseEnable),
       .clock_in(clock_in), .reset_in(reset_in)
       );

endmodule

module SlowEnableGen (frame_enable_out, chase_enable_out, reset_in, clock_in);
   output frame_enable_out, chase_enable_out;
   input  clock_in, reset_in;

   wire [23:00] Heartbeat;
   Heartbeat divider (.heartbeat_out(Heartbeat), .clock_in(clock_in), .reset_in(reset_in));
   RisingEdgeDetect synch_frame (.rising_edge_out(frame_enable_out), .sig_in(Heartbeat[17]), .clock_in(clock_in));
   RisingEdgeDetect synch_chase (.rising_edge_out(chase_enable_out), .sig_in(Heartbeat[18]), .clock_in(clock_in));
endmodule

module Chaser (LEDs_out, done_out, reset_in, chase_enable_in, clock_in);
   output [07:00] LEDs_out;
   output         done_out;
   input          reset_in, chase_enable_in, clock_in;

   reg [08:00]    ChaseRegister;
   assign done_out = ~ (| ChaseRegister);
   assign LEDs_out[07:00] = ChaseRegister[08:01];

   always @ (posedge clock_in) begin
      if (reset_in) begin
         ChaseRegister <= 1;
      end else begin
         if (chase_enable_in) ChaseRegister <= ChaseRegister << 1;
      end
   end
endmodule

module LEDBank (LEDs_out, signals_in, frame_enable_in,
                chase_enable_in, clock_in, reset_in );
   output [07:00] LEDs_out;
   input [07:00]  signals_in;
   input          frame_enable_in, chase_enable_in, clock_in, reset_in;

   wire [07:00]   SplashLEDs, LEDState, SynchSignals;
   wire           AllFadesDone, SplashDone;
   wire [07:00]   LED_done;

   assign LEDState = (SplashDone)? SynchSignals : SplashLEDs;
   assign AllFadesDone = & LED_done;

   Chaser cool_effect
      (
       .LEDs_out(SplashLEDs), .done_out(ChaseDone),
       .reset_in(reset_in), .chase_enable_in(chase_enable_in),
       .clock_in(clock_in)
       );
   FDR ChaseFD
      (
       .D((ChaseDone & AllFadesDone) | SplashDone),
       .Q(SplashDone), .R(reset_in), .C(clock_in)
       );

   //
   // Synchronization:
   AsyncEdgeTrap trap0 (.signal_out(SynchSignals[0]), .signal_in(signals_in[0]), .clock_in(clock_in));
   AsyncEdgeTrap trap1 (.signal_out(SynchSignals[1]), .signal_in(signals_in[1]), .clock_in(clock_in));
   AsyncEdgeTrap trap2 (.signal_out(SynchSignals[2]), .signal_in(signals_in[2]), .clock_in(clock_in));
   AsyncEdgeTrap trap3 (.signal_out(SynchSignals[3]), .signal_in(signals_in[3]), .clock_in(clock_in));
   AsyncEdgeTrap trap4 (.signal_out(SynchSignals[4]), .signal_in(signals_in[4]), .clock_in(clock_in));
   AsyncEdgeTrap trap5 (.signal_out(SynchSignals[5]), .signal_in(signals_in[5]), .clock_in(clock_in));
   AsyncEdgeTrap trap6 (.signal_out(SynchSignals[6]), .signal_in(signals_in[6]), .clock_in(clock_in));
   AsyncEdgeTrap trap7 (.signal_out(SynchSignals[7]), .signal_in(signals_in[7]), .clock_in(clock_in));

   //
   // Faders:
   LED_Fader fade0 ( .LED_out(LEDs_out[0]), .done_out(LED_done[0]), .signal_in(LEDState[0]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade1 ( .LED_out(LEDs_out[1]), .done_out(LED_done[1]), .signal_in(LEDState[1]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade2 ( .LED_out(LEDs_out[2]), .done_out(LED_done[2]), .signal_in(LEDState[2]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade3 ( .LED_out(LEDs_out[3]), .done_out(LED_done[3]), .signal_in(LEDState[3]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade4 ( .LED_out(LEDs_out[4]), .done_out(LED_done[4]), .signal_in(LEDState[4]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade5 ( .LED_out(LEDs_out[5]), .done_out(LED_done[5]), .signal_in(LEDState[5]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade6 ( .LED_out(LEDs_out[6]), .done_out(LED_done[6]), .signal_in(LEDState[6]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
   LED_Fader fade7 ( .LED_out(LEDs_out[7]), .done_out(LED_done[7]), .signal_in(LEDState[7]), .frame_enable_in(frame_enable_in), .follow_mode_in(1'b0), .clock_in(clock_in), .reset_in(reset_in));
endmodule

module SwitchDebounce (switch_out, update_out, switch_in,
                       frame_enable_in, clock_in, reset_in
                       );

   output [39:00] switch_out;
   output         update_out;
   input [39:00]  switch_in;
   input          frame_enable_in, clock_in, reset_in;

   wire [39:00]   Switch;
   LevelDetect sync_switch00 (.sig_level_out(Switch[00]), .sig_in(switch_in[00]), .clock_in(clock_in));
   LevelDetect sync_switch01 (.sig_level_out(Switch[01]), .sig_in(switch_in[01]), .clock_in(clock_in));
   LevelDetect sync_switch02 (.sig_level_out(Switch[02]), .sig_in(switch_in[02]), .clock_in(clock_in));
   LevelDetect sync_switch03 (.sig_level_out(Switch[03]), .sig_in(switch_in[03]), .clock_in(clock_in));
   LevelDetect sync_switch04 (.sig_level_out(Switch[04]), .sig_in(switch_in[04]), .clock_in(clock_in));
   LevelDetect sync_switch05 (.sig_level_out(Switch[05]), .sig_in(switch_in[05]), .clock_in(clock_in));
   LevelDetect sync_switch06 (.sig_level_out(Switch[06]), .sig_in(switch_in[06]), .clock_in(clock_in));
   LevelDetect sync_switch07 (.sig_level_out(Switch[07]), .sig_in(switch_in[07]), .clock_in(clock_in));
   LevelDetect sync_switch08 (.sig_level_out(Switch[08]), .sig_in(switch_in[08]), .clock_in(clock_in));
   LevelDetect sync_switch09 (.sig_level_out(Switch[09]), .sig_in(switch_in[09]), .clock_in(clock_in));
   LevelDetect sync_switch10 (.sig_level_out(Switch[10]), .sig_in(switch_in[10]), .clock_in(clock_in));
   LevelDetect sync_switch11 (.sig_level_out(Switch[11]), .sig_in(switch_in[11]), .clock_in(clock_in));
   LevelDetect sync_switch12 (.sig_level_out(Switch[12]), .sig_in(switch_in[12]), .clock_in(clock_in));
   LevelDetect sync_switch13 (.sig_level_out(Switch[13]), .sig_in(switch_in[13]), .clock_in(clock_in));
   LevelDetect sync_switch14 (.sig_level_out(Switch[14]), .sig_in(switch_in[14]), .clock_in(clock_in));
   LevelDetect sync_switch15 (.sig_level_out(Switch[15]), .sig_in(switch_in[15]), .clock_in(clock_in));
   LevelDetect sync_switch16 (.sig_level_out(Switch[16]), .sig_in(switch_in[16]), .clock_in(clock_in));
   LevelDetect sync_switch17 (.sig_level_out(Switch[17]), .sig_in(switch_in[17]), .clock_in(clock_in));
   LevelDetect sync_switch18 (.sig_level_out(Switch[18]), .sig_in(switch_in[18]), .clock_in(clock_in));
   LevelDetect sync_switch19 (.sig_level_out(Switch[19]), .sig_in(switch_in[19]), .clock_in(clock_in));
   LevelDetect sync_switch20 (.sig_level_out(Switch[20]), .sig_in(switch_in[20]), .clock_in(clock_in));
   LevelDetect sync_switch21 (.sig_level_out(Switch[21]), .sig_in(switch_in[21]), .clock_in(clock_in));
   LevelDetect sync_switch22 (.sig_level_out(Switch[22]), .sig_in(switch_in[22]), .clock_in(clock_in));
   LevelDetect sync_switch23 (.sig_level_out(Switch[23]), .sig_in(switch_in[23]), .clock_in(clock_in));
   LevelDetect sync_switch24 (.sig_level_out(Switch[24]), .sig_in(switch_in[24]), .clock_in(clock_in));
   LevelDetect sync_switch25 (.sig_level_out(Switch[25]), .sig_in(switch_in[25]), .clock_in(clock_in));
   LevelDetect sync_switch26 (.sig_level_out(Switch[26]), .sig_in(switch_in[26]), .clock_in(clock_in));
   LevelDetect sync_switch27 (.sig_level_out(Switch[27]), .sig_in(switch_in[27]), .clock_in(clock_in));
   LevelDetect sync_switch28 (.sig_level_out(Switch[28]), .sig_in(switch_in[28]), .clock_in(clock_in));
   LevelDetect sync_switch29 (.sig_level_out(Switch[29]), .sig_in(switch_in[29]), .clock_in(clock_in));
   LevelDetect sync_switch30 (.sig_level_out(Switch[30]), .sig_in(switch_in[30]), .clock_in(clock_in));
   LevelDetect sync_switch31 (.sig_level_out(Switch[31]), .sig_in(switch_in[31]), .clock_in(clock_in));
   LevelDetect sync_switch32 (.sig_level_out(Switch[32]), .sig_in(switch_in[32]), .clock_in(clock_in));
   LevelDetect sync_switch33 (.sig_level_out(Switch[33]), .sig_in(switch_in[33]), .clock_in(clock_in));
   LevelDetect sync_switch34 (.sig_level_out(Switch[34]), .sig_in(switch_in[34]), .clock_in(clock_in));
   LevelDetect sync_switch35 (.sig_level_out(Switch[35]), .sig_in(switch_in[35]), .clock_in(clock_in));
   LevelDetect sync_switch36 (.sig_level_out(Switch[36]), .sig_in(switch_in[36]), .clock_in(clock_in));
   LevelDetect sync_switch37 (.sig_level_out(Switch[37]), .sig_in(switch_in[37]), .clock_in(clock_in));
   LevelDetect sync_switch38 (.sig_level_out(Switch[38]), .sig_in(switch_in[38]), .clock_in(clock_in));
   LevelDetect sync_switch39 (.sig_level_out(Switch[39]), .sig_in(switch_in[39]), .clock_in(clock_in));

   reg [39:00]    OutputRegister, OutputRegister__next;
   reg [39:00]    SettleRegister, SettleRegister__next;
   reg            Settled, Settled__next;
   reg            Update, Update__next;

   assign switch_out = OutputRegister;
   assign update_out = Update;

   always @ (SettleRegister or Settled or Switch or frame_enable_in) begin
      SettleRegister__next <= SettleRegister;
      Settled__next <= Settled;
      if (SettleRegister != Switch) Settled__next <= 0;
      if (frame_enable_in) begin
         SettleRegister__next <= Switch;
         Settled__next <= 1;
      end
   end

   always @ (Switch or OutputRegister or Update or Settled or frame_enable_in) begin
      OutputRegister__next <= OutputRegister;
      Update__next <= 0;
      if (frame_enable_in & Settled) begin
         OutputRegister__next <= Switch;
         if (Switch != OutputRegister) Update__next <= 1;
      end
   end

   always @ (posedge clock_in) begin
      if (reset_in) begin
         OutputRegister <= 0;
         SettleRegister <= 0;
         Settled <= 0;
         Update <= 0;
      end else begin
         OutputRegister <= OutputRegister__next;
         SettleRegister <= SettleRegister__next;
         Settled <= Settled__next;
         Update <= Update__next;
      end
   end
endmodule

module SynchDCMLocked (locked_out, locked_in, clock_in);
   output locked_out;
   input  locked_in, clock_in;

   FDC synch_0 (.D(locked_in), .Q(synch_out_0), .CLR(~locked_in), .C(clock_in));
   FDC synch_1 (.D(synch_out_0), .Q(locked_out), .CLR(~locked_in), .C(clock_in));
endmodule

`endif