virtexiiplib.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  VirtexIIpLib.v
//      Version:  2.2
//         Date:  05/14/03
//        Model:  VirtexIIp specific devices usefull for developing VirtexIIp
//                parallel bit error rate tester.
//
//      Company:  Xilinx, Inc.
//  Contributor:  Mike Matera
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////

`ifdef VIRTEXIIPLIB `else 
`define VIRTEXIIPLIB

module Heartbeat (heartbeat_out, clock_in, reset_in);
   output [23:00] heartbeat_out;
   input          clock_in, reset_in;
   
   reg [23:00]    heartbeat_out;
   wire [23:00]   heartbeat_out__next;
   assign heartbeat_out__next = heartbeat_out + 1;
   always @ (posedge clock_in) begin
      if (reset_in) heartbeat_out <= 0;
      else heartbeat_out <= heartbeat_out__next;
   end
endmodule

module EdgeDetect (edge_out, sig_in, clock_in);
   output edge_out;
   input  sig_in, clock_in;

   wire   synch_out_0, synch_out_1;
   FD synch_0 (.D(sig_in), .Q(synch_out_0), .C(clock_in));
   FD synch_1 (.D(synch_out_0), .Q(synch_out_1), .C(clock_in));

   wire   sig_edge;
   assign sig_edge = synch_out_0 ^ synch_out_1;

   FD synch_e (.D(sig_edge), .Q(edge_out), .C(clock_in));   
endmodule

module RisingEdgeDetect (rising_edge_out, sig_in, clock_in);
   output rising_edge_out;
   input  sig_in, clock_in;
   
   wire   synch_out_0, synch_out_1;
   FD synch_0 (.D(sig_in), .Q(synch_out_0), .C(clock_in));
   FD synch_1 (.D(synch_out_0), .Q(synch_out_1), .C(clock_in));

   wire   sig_edge;
   assign sig_edge = synch_out_0 & ~synch_out_1;

   FD synch_e (.D(sig_edge), .Q(rising_edge_out), .C(clock_in));   
endmodule

module LevelDetect (sig_level_out, sig_in, clock_in);
   output sig_level_out;
   input  sig_in, clock_in;

   wire   synch_out_0, synch_out_1;
   FD synch_0 (.D(sig_in), .Q(synch_out_0), .C(clock_in));
   FD synch_1 (.D(synch_out_0), .Q(sig_level_out), .C(clock_in));
endmodule

module Synchronizer (sig_rise_out, sig_fall_out, sig_level_out, sig_in, clock_in);
   output sig_rise_out, sig_fall_out, sig_level_out;
   input  sig_in, clock_in;

   wire   synch_out_0, synch_out_1;
   FD synch_0 (.D(sig_in), .Q(synch_out_0), .C(clock_in));
   FD synch_1 (.D(synch_out_0), .Q(synch_out_1), .C(clock_in));

   wire   sig_rise, sig_fall;
   assign sig_rise = synch_out_0 & ~synch_out_1;
   assign sig_fall = ~synch_out_0 & synch_out_1;
   assign sig_level_out = synch_out_1;
   
   FD synch_r (.D(sig_rise), .Q(sig_rise_out), .C(clock_in));   
   FD synch_f (.D(sig_fall), .Q(sig_fall_out), .C(clock_in));   
endmodule

module FDRE32 (Q_out, D_in, CE_in, reset_in, clock_in);
   output [31:00] Q_out;
   input [31:00]  D_in;
   input          CE_in, reset_in, clock_in;
   
   FDRE ff00 (.Q(Q_out[00]), .D(D_in[00]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff01 (.Q(Q_out[01]), .D(D_in[01]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff02 (.Q(Q_out[02]), .D(D_in[02]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff03 (.Q(Q_out[03]), .D(D_in[03]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff04 (.Q(Q_out[04]), .D(D_in[04]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff05 (.Q(Q_out[05]), .D(D_in[05]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff06 (.Q(Q_out[06]), .D(D_in[06]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff07 (.Q(Q_out[07]), .D(D_in[07]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff08 (.Q(Q_out[08]), .D(D_in[08]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff09 (.Q(Q_out[09]), .D(D_in[09]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff10 (.Q(Q_out[10]), .D(D_in[10]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff11 (.Q(Q_out[11]), .D(D_in[11]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff12 (.Q(Q_out[12]), .D(D_in[12]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff13 (.Q(Q_out[13]), .D(D_in[13]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff14 (.Q(Q_out[14]), .D(D_in[14]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff15 (.Q(Q_out[15]), .D(D_in[15]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff16 (.Q(Q_out[16]), .D(D_in[16]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff17 (.Q(Q_out[17]), .D(D_in[17]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff18 (.Q(Q_out[18]), .D(D_in[18]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff19 (.Q(Q_out[19]), .D(D_in[19]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff20 (.Q(Q_out[20]), .D(D_in[20]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff21 (.Q(Q_out[21]), .D(D_in[21]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff22 (.Q(Q_out[22]), .D(D_in[22]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff23 (.Q(Q_out[23]), .D(D_in[23]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff24 (.Q(Q_out[24]), .D(D_in[24]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff25 (.Q(Q_out[25]), .D(D_in[25]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff26 (.Q(Q_out[26]), .D(D_in[26]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff27 (.Q(Q_out[27]), .D(D_in[27]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff28 (.Q(Q_out[28]), .D(D_in[28]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff29 (.Q(Q_out[29]), .D(D_in[29]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff30 (.Q(Q_out[30]), .D(D_in[30]), .R(reset_in), .CE(CE_in), .C(clock_in));
   FDRE ff31 (.Q(Q_out[31]), .D(D_in[31]), .R(reset_in), .CE(CE_in), .C(clock_in));   
endmodule
 
module AsyncEdgeTrap (signal_out, signal_in, clock_in);
   output signal_out;
   input  signal_in, clock_in;

   wire   Catch1, Catch0, signal_out__synch0;

   FJK synch0 (.Q(signal_out__synch0), .J(Catch1), .K(Catch0), .C(clock_in));
   FDP catch1 (.Q(Catch1), .D(1'b0), .PRE(signal_in), .C(clock_in));
   FDP catch0 (.Q(Catch0), .D(1'b0), .PRE(~signal_in), .C(clock_in));
   FD synch1 (.Q(signal_out), .D(signal_out__synch0), .C(clock_in));
endmodule

module FJK (Q, J, K, C);
   output Q;
   input  J, K, C;
   wire   NextValue = (~J & ~K & Q) + (J & ~K) + (J & K & ~Q);
   FD fjk (.Q(Q), .D(NextValue), .C(C));
endmodule

module SafeSignalGenerator (framelength_out, pattern_out, enable_in, reset_in, clock_in);
   output [20:00] framelength_out;
   output [19:00] pattern_out;
   input          enable_in, reset_in, clock_in;

   reg [03:00]    BitBarrel;
   assign pattern_out = {BitBarrel, BitBarrel, BitBarrel, BitBarrel, BitBarrel};
   assign framelength_out = 21'd5;
   
   always @ (posedge clock_in) begin
      if (reset_in) BitBarrel <= 4'b0011;
      else begin
         if (enable_in) begin
            BitBarrel[0] <= BitBarrel[3];
            BitBarrel[1] <= BitBarrel[0];
            BitBarrel[2] <= BitBarrel[1];
            BitBarrel[3] <= BitBarrel[2];
         end
      end
   end
endmodule

module Registering (clock_in, sig_in, sig_out);
   input          clock_in;
   input  [01:00] sig_in;
   output [01:00] sig_out;

   reg [01:00]    sig_out;
   
   always @ (posedge clock_in) 
          sig_out <= sig_in;

endmodule


//-------------------------------------------------------------------
//
//  ICON Pro core module declaration
//
//-------------------------------------------------------------------
module icon 
  (
      control0
   ) /* synthesis syn_black_box syn_noprune=1 */;
  output [35:0] control0;
 endmodule

//-------------------------------------------------------------------
//
//  ILA Pro core module declaration
//
//-------------------------------------------------------------------
module ila
  (
    control,
    clk,
    data,
    trig0
  ) /* synthesis syn_black_box syn_noprune=1 */;
  input [35:0] control;
  input clk;
  input [40:0] data;
  input [0:0] trig0;
endmodule

   
`endif