plb_mgtbert.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  plb_mgtbert.v
//      Version:  2.4
//         Date:  2004-03-15
//        Model:  PLB MGT BERT Module. This module interfaces MGT BERT IP to
//                PLB IPIF
//
//      Company:  Xilinx, Inc.
//  Contributor:  Systems Engineering Group
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////

  
module plb_mgtbert (
  PLB_Clk,
  PLB_Rst,
// PLB Slave Interface
  // Transfer Qualifiers Signals
  // Inputs
  PLB_PAValid,
  PLB_busLock,
  PLB_masterID,
  PLB_RNW,
  PLB_BE,
  PLB_size,
  PLB_type,
  PLB_MSize,
  PLB_compress,
  PLB_guarded,
  PLB_ordered,
  PLB_lockErr,
  PLB_abort,
  PLB_ABus,
  // Outputs
  Sl_addrAck,
  Sl_wait,
  Sl_SSize,
  Sl_rearbitrate,
  Sl_MBusy,
  Sl_MErr,
  // Adress Pipelining Signals
  // Inputs
  PLB_SAValid,
  PLB_rdPrim,
  PLB_wrPrim,
  // Write Data Bus Signals
  // Inputs
  PLB_wrDBus,
  PLB_wrBurst,
  // Outputs
  Sl_wrDAck,
  Sl_wrComp,
  Sl_wrBTerm,
  // Read Data Bus Signals
  // Inputs
  PLB_rdBurst,
  // Outputs
  Sl_rdDBus,
  Sl_rdWdAddr,
  Sl_rdDAck,
  Sl_rdComp,
  Sl_rdBTerm,
  //
  PLB_pendPri,
  PLB_pendReq,
  PLB_reqPri,
  // BERT Signals
  LEDs,
  DIPs,
  PBUTTONs,
  TXN,
  TXP,
  RXN,
  RXP,
  BREF_CLK_P,
  BREF_CLK_N,
  CLKOUTs
  );

  parameter C_NUM_MASTERS = 2;
  parameter C_BASEADDR = 32'ha0010000;
  parameter C_HIGHADDR = 32'ha00100ff;
  parameter C_PLB_DWIDTH = 64;
  parameter C_PLB_AWIDTH = 32;
  parameter C_PLB_MID_WIDTH = 1;
  
// Port Declarations ************************************************

  input         PLB_Clk;
  input         PLB_Rst;
// PLB Slave Interface
  // Transfer Qualifiers Signals
  input         PLB_PAValid;
  input         PLB_busLock;
  input  [0:C_PLB_MID_WIDTH-1]  PLB_masterID;
  input         PLB_RNW;
  input  [0:7]  PLB_BE;
  input  [0:3]  PLB_size;
  input  [0:2]  PLB_type;
  input  [0:1]  PLB_MSize;
  input         PLB_compress;
  input         PLB_guarded;
  input         PLB_ordered;
  input         PLB_lockErr;
  input         PLB_abort;
  input  [0:31] PLB_ABus;
  output        Sl_addrAck;
  output        Sl_wait;
  output [0:1]  Sl_SSize;
  output        Sl_rearbitrate;
  output [0:C_NUM_MASTERS-1] Sl_MBusy;
  output [0:C_NUM_MASTERS-1] Sl_MErr;
  // Adress Pipelining Signals
  input         PLB_SAValid;
  input         PLB_rdPrim;
  input         PLB_wrPrim;
  // Write Data Bus Signals
  input  [0:63] PLB_wrDBus;
  input         PLB_wrBurst;
  output        Sl_wrDAck;
  output        Sl_wrComp;
  output        Sl_wrBTerm;
  // Read Data Bus Signals
  input         PLB_rdBurst;
  output [0:63] Sl_rdDBus;
  output [0:3]  Sl_rdWdAddr;
  output        Sl_rdDAck;
  output        Sl_rdComp;
  output        Sl_rdBTerm;
  //
  input [0:1]   PLB_pendPri;
  input         PLB_pendReq;
  input [0:1]   PLB_reqPri;  
  // BERT Signals
  output [15:0]  LEDs;
  input  [3:0]   PBUTTONs;
  input  [15:0]  DIPs;
  output [3:0]   TXN;
  output [3:0]   TXP;
  input  [3:0]   RXN;
  input  [3:0]   RXP;
  inout  [3:0]   BREF_CLK_P, BREF_CLK_N;
  output [2:0]   CLKOUTs;

// Signal Declarations ***********************************************

  wire [0:31]   addr;
  wire [0:3]    byte_en;
  wire          clk;
  wire          rd_ack;
  wire          rd_req;
  reg           rd_req_d1;
  reg           rd_req_d2;
  reg  [0:31]   read_data;
  wire          reset;
  wire          sram_CE;
  wire          wr_ack;
  wire          wr_req;
  reg           wr_req_d1;
  reg           wr_req_d2;
  wire [0:31]   write_data;
  wire [0:3]    addr_lean;

// BERT Signal Declarations ***********************************************
  wire [27:0]   DIPs_final1;
  wire [7:0]    DIPs_final2;
  reg  [27:0]   DIPs_ppc1;
  reg  [7:0]    DIPs_ppc2;
  wire [03:0]   PBUTTONs_final;
  reg  [03:0]   PBUTTONs_ppc;
  wire [95:0]   total_frames;
  wire [63:0]   dropped_frames;
  wire [79:0]   error_factor;
  wire [28:0]   bert_status;
  wire [63:0]   bec_count_out;


// Parameter Declarations ********************************************
  
  parameter     C_LSB_ADDR  = 25;

// Module Declarations ***********************************************

plb_ipif_slv_sram #(C_LSB_ADDR, C_BASEADDR) IPIF(
  .SYS_plbClk(PLB_Clk),
  .SYS_plbReset(PLB_Rst),
// PLB Slave Interface
  // Transfer Qualifiers Signals
  // Inputs
  .PLB_PAValid(PLB_PAValid),
  .PLB_busLock(PLB_busLock),
  .PLB_masterID({3'b0,PLB_masterID}),
  .PLB_RNW(PLB_RNW),
  .PLB_BE(PLB_BE),
  .PLB_size(PLB_size),
  .PLB_type(PLB_type),
  .PLB_MSize(PLB_MSize),
  .PLB_compress(PLB_compress),
  .PLB_guarded(PLB_guarded),
  .PLB_ordered(PLB_ordered),
  .PLB_lockErr(PLB_lockErr),
  .PLB_abort(PLB_abort),
  .PLB_ABus(PLB_ABus),
  // Outputs
  .Sl_addrAck(Sl_addrAck),
  .Sl_wait(Sl_wait),
  .Sl_SSize(Sl_SSize),
  .Sl_rearbitrate(Sl_rearbitrate),
  .Sl_MBusy(Sl_MBusy[0:C_NUM_MASTERS-1]),
  .Sl_MErr(Sl_MErr[0:C_NUM_MASTERS-1]),
  // Adress Pipelining Signals
  // Inputs
  .PLB_SAValid(PLB_SAValid),
  .PLB_rdPrim(PLB_rdPrim),
  .PLB_wrPrim(PLB_wrPrim),
  // Write Data Bus Signals
  // Inputs
  .PLB_wrDBus(PLB_wrDBus),
  .PLB_wrBurst(PLB_wrBurst),
  // Outputs
  .Sl_wrDAck(Sl_wrDAck),
  .Sl_wrComp(Sl_wrComp),
  .Sl_wrBTerm(Sl_wrBTerm),
  // Read Data Bus Signals
  // Inputs
  .PLB_rdBurst(PLB_rdBurst),
  // Outputs
  .Sl_rdDBus(Sl_rdDBus),
  .Sl_rdWdAddr(Sl_rdWdAddr),
  .Sl_rdDAck(Sl_rdDAck),
  .Sl_rdComp(Sl_rdComp),
  .Sl_rdBTerm(Sl_rdBTerm),
  // Ouput to IP Signals
  .Bus2IP_Clk(clk),
  .Bus2IP_Reset(reset),
  .Bus2IP_Addr(addr),
  .Bus2IP_BE(byte_en),
  .Bus2IP_Data(write_data),
  .Bus2IP_RdReq(rd_req),
  .Bus2IP_SRAM_CE(sram_CE),
  .Bus2IP_WrReq(wr_req),
  // Input from IP Signals
  .IP2Bus_Data(read_data),
  .IP2Bus_Error(1'b0),
  .IP2Bus_RdAck(rd_ack),
  .IP2Bus_Retry(1'b0),
  .IP2Bus_ToutSup(1'b0),
  .IP2Bus_WrAck(wr_ack)
 );


assign addr_lean = addr[26:29];

always @ (posedge clk)
begin
 if (rd_req & sram_CE) begin
  case (addr_lean)
    4'b0000:  //0xA0010000
    begin
      read_data <= {16'b0,total_frames[47:32]};
    end
    4'b0001 : //0xA0010004
    begin
      read_data <= total_frames[31:0];    
    end
    4'b0010:  //0xA0010008
    begin
      read_data <= dropped_frames[31:0];
    end
    4'b0011 : //0xA001000C
    begin
      read_data <= {16'b0,total_frames[95:80]};
    end
    4'b0100 : //0xA0010010
    begin
      read_data <= total_frames[79:48];    
    end
    4'b0101 : //0xA0010014
    begin
      read_data <= dropped_frames[63:32];
    end
    4'b0110 : //0xA0010018
    begin
      read_data <= {3'b0,bert_status};
    end
    4'b0111:  //0xA001001C
    begin
      read_data <= {24'b0,error_factor[39:32]};
    end
    4'b1000 : //0xA0010020
    begin
      read_data <= error_factor[31:0];    
    end
    4'b1001 : //0xA0010024
    begin
      read_data <= {24'b0,error_factor[79:72]};
    end
    4'b1010 : //0xA0010028
    begin
      read_data <= error_factor[71:40];    
    end
    4'b1011 : //0xA001002C
    begin
      read_data <= bec_count_out[31:0];
    end
    4'b1100 : //0xA0010030
    begin
      read_data <= bec_count_out[63:32];
    end
    default:
      read_data <= 32'b0;
    endcase
  end
end


// Main body of code *************************************************

always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc1[7:0] = 8'b00000000;
 else if (wr_ack && byte_en[3] && addr_lean == 4'b0000) //0xA0010000
   DIPs_ppc1[7:0] = write_data[24:31];
end

always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc1[15:8] = 8'b00000000;
 else if (wr_ack && byte_en[2] && addr_lean == 4'b0000)
   DIPs_ppc1[15:8] = write_data[16:23];
end

always @ (posedge clk)
begin
 if (reset)
   PBUTTONs_ppc[3:0] = 4'b0000;
 else if (wr_ack && byte_en[1] && addr_lean == 4'b0000 )
   PBUTTONs_ppc[3:0] = write_data[12:15];
end

always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc1[19:16] = 4'b0000;
 else if (wr_ack && byte_en[1] && addr_lean == 4'b0000)
   DIPs_ppc1[19:16] = write_data[8:11];
end

//Idle MGT Control
always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc1[27:20] = 8'b00000000;
 else if (wr_ack && byte_en[0] && addr_lean == 4'b0000)
   DIPs_ppc1[27:20] = write_data[0:7];
end

//Programmable Delay
always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc2[3:0] = 4'b0000;
 else if (wr_ack && byte_en[1] && (addr_lean == 4'b0001))//0xA0010004
   DIPs_ppc2[3:0] = write_data[12:15];
end


//DIPs_ppc2[5:4] : LoopBack
//DIPs_ppc2[7:6] : Unused
always @ (posedge clk)
begin
 if (reset)
   DIPs_ppc2[7:4] = 4'b0000;
 else if (wr_ack && byte_en[1] && (addr_lean == 4'b0001))//0xA0010004
   DIPs_ppc2[7:4] = write_data[8:11];
end

// Main body of code *************************************************

// logic to handle reads
always @(posedge clk)
begin
  if (rd_ack) begin
    rd_req_d1 <= 1'b0;
    rd_req_d2 <= 1'b0;
  end
  else begin
    rd_req_d1 <= rd_req;
    rd_req_d2 <= rd_req_d1;
  end
end

assign rd_ack = rd_req_d1 & ~rd_req_d2;

always @(posedge clk)
begin
  if (wr_ack) begin
    wr_req_d1 <= 1'b0;
    wr_req_d2 <= 1'b0;
  end
  else begin
    wr_req_d1 <= wr_req;
    wr_req_d2 <= wr_req_d1;
  end
end

assign wr_ack = wr_req_d1 & ~wr_req_d2;

///////////////////////////////////////////////////////////////////////////////
// MGT Parallel BERT Module
///////////////////////////////////////////////////////////////////////////////
assign DIPs_final1[15:0] = DIPs[12] ? DIPs[15:0] :  DIPs_ppc1[15:0];
assign DIPs_final1[19:16] = DIPs[12] ? DIPs[7:4] :  DIPs_ppc1[19:16];
assign DIPs_final1[27:20] = DIPs_ppc1[27:20];
assign DIPs_final2[7:0] = DIPs_ppc2[7:0];
assign PBUTTONs_final = PBUTTONs | PBUTTONs_ppc;

MGTBoardBERT MGTBoardBERT
(
    .serial_n_out(TXN[01:00]),
    .serial_p_out(TXP[01:00]),
    .serial_n_out_idle(TXN[03:02]),
    .serial_p_out_idle(TXP[03:02]),
    .serial_n_in(RXN[01:00]),
    .serial_p_in(RXP[01:00]),
    .serial_n_in_idle(RXN[03:02]),
    .serial_p_in_idle(RXP[03:02]),
    .bec_count_out(bec_count_out),
    .LEDs_out(LEDs),
    .DIP_switch_in({DIPs_final2,DIPs_final1}),
    .Push_buttons_in(PBUTTONs_final),
    .BREF_CLK_P (BREF_CLK_P),
    .BREF_CLK_N (BREF_CLK_N),
    .rt_clock_in(PLB_Clk),
    .recovered_clocks_out(CLKOUTs),
    .total_frames_out(total_frames),
    .dropped_frames_out(dropped_frames),
    .error_factor_out(error_factor),    
    .status(bert_status)        );


endmodule