patternlib.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

   input          length_in, advance_in, reset_in, clock_in;
   
   reg [06:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [06:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX07 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX07 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX07 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX07 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX07 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX07 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX07 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX07 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX07 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX07 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX07 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX07 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX07 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX07 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX07 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX07 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX07 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX07 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX07 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX07 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 7'b1111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[06], ix01[06], ix02[06], ix03[06], ix04[06], ix05[06], ix06[06], ix07[06], ix08[06], ix09[06], ix10[06], ix11[06], ix12[06], ix13[06], ix14[06], ix15[06], ix16[06], ix17[06], ix18[06], ix19[06]};
      end
   end
endmodule

//----------------------------------------------------------------
//
// III. Intermediate Expression Section.
//   A. Contents:
//     1. IX31: 31-bit implementation
//     2. IX29: 29-bit implementation
//     3. IX23: 23-bit implementation
//     4. IX20: 20-bit implementation
//     5. IX15: 15-bit implementation
//     6. IX11: 11-bit implementation
//     6. IX09:  9-bit implementation
//     6. IX07:  7-bit implementation
//
//   B. Port Summary.
//
//     exp_out[19:00] (asynchronous)
//        Value of the LFSR at time T(n+1).
//
//     exp_in[19:00] (asynchronous)
//        Value of the LFSR at time T(n).
//
//     poly_in[XX:00] (asynchronous)
//        Number representing the LFSR's polynomial.
//
//     length_in (asynchronous)
//        High if the LFSR should be maximal length.
//
//----------------------------------------------------------------
`ifdef WITH_TYPE1 
module IX32 (exp_out, exp_in, poly_in, length_in);
   output [31:00] exp_out;
   input [31:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[31]) ^
                        (exp_in[01] & poly_in[30]) ^
                        (exp_in[02] & poly_in[29]) ^
                        (exp_in[03] & poly_in[28]) ^
                        (exp_in[04] & poly_in[27]) ^
                        (exp_in[05] & poly_in[26]) ^
                        (exp_in[06] & poly_in[25]) ^
                        (exp_in[07] & poly_in[24]) ^
                        (exp_in[08] & poly_in[23]) ^
                        (exp_in[09] & poly_in[22]) ^
                        (exp_in[10] & poly_in[21]) ^
                        (exp_in[11] & poly_in[20]) ^
                        (exp_in[12] & poly_in[19]) ^
                        (exp_in[13] & poly_in[18]) ^
                        (exp_in[14] & poly_in[17]) ^
                        (exp_in[15] & poly_in[16]) ^
                        (exp_in[16] & poly_in[15]) ^
                        (exp_in[17] & poly_in[14]) ^
                        (exp_in[18] & poly_in[13]) ^
                        (exp_in[19] & poly_in[12]) ^
                        (exp_in[20] & poly_in[11]) ^
                        (exp_in[21] & poly_in[10]) ^
                        (exp_in[22] & poly_in[09]) ^
                        (exp_in[23] & poly_in[08]) ^
                        (exp_in[24] & poly_in[07]) ^
                        (exp_in[25] & poly_in[06]) ^
                        (exp_in[26] & poly_in[05]) ^
                        (exp_in[27] & poly_in[04]) ^
                        (exp_in[28] & poly_in[03]) ^
                        (exp_in[29] & poly_in[02]) ^
                        (exp_in[30] & poly_in[01]) ^
                        (exp_in[31] & poly_in[00]) ^ length_in;

   assign exp_out[31:01] = exp_in[30:00];
endmodule

module IX31 (exp_out, exp_in, poly_in, length_in);
   output [30:00] exp_out;
   input [30:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[30]) ^
                        (exp_in[01] & poly_in[29]) ^
                        (exp_in[02] & poly_in[28]) ^
                        (exp_in[03] & poly_in[27]) ^
                        (exp_in[04] & poly_in[26]) ^
                        (exp_in[05] & poly_in[25]) ^
                        (exp_in[06] & poly_in[24]) ^
                        (exp_in[07] & poly_in[23]) ^
                        (exp_in[08] & poly_in[22]) ^
                        (exp_in[09] & poly_in[21]) ^
                        (exp_in[10] & poly_in[20]) ^
                        (exp_in[11] & poly_in[19]) ^
                        (exp_in[12] & poly_in[18]) ^
                        (exp_in[13] & poly_in[17]) ^
                        (exp_in[14] & poly_in[16]) ^
                        (exp_in[15] & poly_in[15]) ^
                        (exp_in[16] & poly_in[14]) ^
                        (exp_in[17] & poly_in[13]) ^
                        (exp_in[18] & poly_in[12]) ^
                        (exp_in[19] & poly_in[11]) ^
                        (exp_in[20] & poly_in[10]) ^
                        (exp_in[21] & poly_in[09]) ^
                        (exp_in[22] & poly_in[08]) ^
                        (exp_in[23] & poly_in[07]) ^
                        (exp_in[24] & poly_in[06]) ^
                        (exp_in[25] & poly_in[05]) ^
                        (exp_in[26] & poly_in[04]) ^
                        (exp_in[27] & poly_in[03]) ^
                        (exp_in[28] & poly_in[02]) ^
                        (exp_in[29] & poly_in[01]) ^
                        (exp_in[30] & poly_in[00]) ^ length_in;

   assign exp_out[30:01] = exp_in[29:00];
endmodule

module IX29 (exp_out, exp_in, poly_in, length_in);
   output [28:00] exp_out;
   input [28:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[28]) ^
                        (exp_in[01] & poly_in[27]) ^
                        (exp_in[02] & poly_in[26]) ^
                        (exp_in[03] & poly_in[25]) ^
                        (exp_in[04] & poly_in[24]) ^
                        (exp_in[05] & poly_in[23]) ^
                        (exp_in[06] & poly_in[22]) ^
                        (exp_in[07] & poly_in[21]) ^
                        (exp_in[08] & poly_in[20]) ^
                        (exp_in[09] & poly_in[19]) ^
                        (exp_in[10] & poly_in[18]) ^
                        (exp_in[11] & poly_in[17]) ^
                        (exp_in[12] & poly_in[16]) ^
                        (exp_in[13] & poly_in[15]) ^
                        (exp_in[14] & poly_in[14]) ^
                        (exp_in[15] & poly_in[13]) ^
                        (exp_in[16] & poly_in[12]) ^
                        (exp_in[17] & poly_in[11]) ^
                        (exp_in[18] & poly_in[10]) ^
                        (exp_in[19] & poly_in[09]) ^
                        (exp_in[20] & poly_in[08]) ^
                        (exp_in[21] & poly_in[07]) ^
                        (exp_in[22] & poly_in[06]) ^
                        (exp_in[23] & poly_in[05]) ^
                        (exp_in[24] & poly_in[04]) ^
                        (exp_in[25] & poly_in[03]) ^
                        (exp_in[26] & poly_in[02]) ^
                        (exp_in[27] & poly_in[01]) ^
                        (exp_in[28] & poly_in[00]) ^ length_in;

   assign exp_out[28:01] = exp_in[27:00];
endmodule

module IX23 (exp_out, exp_in, poly_in, length_in);
   output [22:00] exp_out;
   input [22:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[22]) ^
                        (exp_in[01] & poly_in[21]) ^
                        (exp_in[02] & poly_in[20]) ^
                        (exp_in[03] & poly_in[19]) ^
                        (exp_in[04] & poly_in[18]) ^
                        (exp_in[05] & poly_in[17]) ^
                        (exp_in[06] & poly_in[16]) ^
                        (exp_in[07] & poly_in[15]) ^
                        (exp_in[08] & poly_in[14]) ^
                        (exp_in[09] & poly_in[13]) ^
                        (exp_in[10] & poly_in[12]) ^
                        (exp_in[11] & poly_in[11]) ^
                        (exp_in[12] & poly_in[10]) ^
                        (exp_in[13] & poly_in[09]) ^
                        (exp_in[14] & poly_in[08]) ^
                        (exp_in[15] & poly_in[07]) ^
                        (exp_in[16] & poly_in[06]) ^
                        (exp_in[17] & poly_in[05]) ^
                        (exp_in[18] & poly_in[04]) ^
                        (exp_in[19] & poly_in[03]) ^
                        (exp_in[20] & poly_in[02]) ^
                        (exp_in[21] & poly_in[01]) ^
                        (exp_in[22] & poly_in[00]) ^ length_in;


   assign exp_out[22:01] = exp_in[21:00];
endmodule

module IX20 (exp_out, exp_in, poly_in, length_in);
   output [19:00] exp_out;
   input [19:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[19]) ^
                        (exp_in[01] & poly_in[18]) ^
                        (exp_in[02] & poly_in[17]) ^
                        (exp_in[03] & poly_in[16]) ^
                        (exp_in[04] & poly_in[15]) ^
                        (exp_in[05] & poly_in[14]) ^
                        (exp_in[06] & poly_in[13]) ^
                        (exp_in[07] & poly_in[12]) ^
                        (exp_in[08] & poly_in[11]) ^
                        (exp_in[09] & poly_in[10]) ^
                        (exp_in[10] & poly_in[09]) ^
                        (exp_in[11] & poly_in[08]) ^
                        (exp_in[12] & poly_in[07]) ^
                        (exp_in[13] & poly_in[06]) ^
                        (exp_in[14] & poly_in[05]) ^
                        (exp_in[15] & poly_in[04]) ^
                        (exp_in[16] & poly_in[03]) ^
                        (exp_in[17] & poly_in[02]) ^
                        (exp_in[18] & poly_in[01]) ^
                        (exp_in[19] & poly_in[00]) ^ length_in;

   assign exp_out[19:01] = exp_in[18:00];
endmodule

module IX15 (exp_out, exp_in, poly_in, length_in);
   output [14:00] exp_out;
   input [14:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[14]) ^
                        (exp_in[01] & poly_in[13]) ^
                        (exp_in[02] & poly_in[12]) ^
                        (exp_in[03] & poly_in[11]) ^
                        (exp_in[04] & poly_in[10]) ^
                        (exp_in[05] & poly_in[09]) ^
                        (exp_in[06] & poly_in[08]) ^
                        (exp_in[07] & poly_in[07]) ^
                        (exp_in[08] & poly_in[06]) ^
                        (exp_in[09] & poly_in[05]) ^
                        (exp_in[10] & poly_in[04]) ^
                        (exp_in[11] & poly_in[03]) ^
                        (exp_in[12] & poly_in[02]) ^
                        (exp_in[13] & poly_in[01]) ^
                        (exp_in[14] & poly_in[00]) ^ length_in;

   assign exp_out[14:01] = exp_in[13:00];
endmodule

module IX11 (exp_out, exp_in, poly_in, length_in);
   output [10:00] exp_out;
   input [10:00]  exp_in, poly_in;
   input          length_in;

   assign exp_out[00] = (exp_in[00] & poly_in[10]) ^
                        (exp_in[01] & poly_in[09]) ^
                        (exp_in[02] & poly_in[08]) ^
                        (exp_in[03] & poly_in[07]) ^
                        (exp_in[04] & poly_in[06]) ^
                        (exp_in[05] & poly_in[05]) ^