patternlib.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[30], ix01[30], ix02[30], ix03[30], ix04[30], ix05[30], ix06[30], ix07[30], ix08[30], ix09[30], ix10[30], ix11[30], ix12[30], ix13[30], ix14[30], ix15[30], ix16[30], ix17[30], ix18[30], ix19[30]};
      end
   end
endmodule

module PRBSGen29(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [28:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [28:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [28:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;
   
   IX29 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX29 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX29 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX29 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX29 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX29 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX29 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX29 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX29 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX29 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX29 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX29 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX29 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX29 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX29 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX29 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX29 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX29 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX29 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX29 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 29'b11111111111111111111111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[28], ix01[28], ix02[28], ix03[28], ix04[28], ix05[28], ix06[28], ix07[28], ix08[28], ix09[28], ix10[28], ix11[28], ix12[28], ix13[28], ix14[28], ix15[28], ix16[28], ix17[28], ix18[28], ix19[28]};
      end
   end
endmodule

module PRBSGen23(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [22:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [22:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [22:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX23 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX23 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX23 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX23 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX23 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX23 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX23 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX23 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX23 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX23 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX23 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX23 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX23 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX23 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX23 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX23 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX23 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX23 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX23 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX23 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 23'b11111111111111111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[22], ix01[22], ix02[22], ix03[22], ix04[22], ix05[22], ix06[22], ix07[22], ix08[22], ix09[22], ix10[22], ix11[22], ix12[22], ix13[22], ix14[22], ix15[22], ix16[22], ix17[22], ix18[22], ix19[22]};
      end
   end
endmodule

module PRBSGen20(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [19:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [19:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [19:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX20 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX20 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX20 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX20 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX20 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX20 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX20 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX20 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX20 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX20 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX20 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX20 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX20 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX20 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX20 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX20 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX20 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX20 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX20 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX20 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 20'b11111111111111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[19], ix01[19], ix02[19], ix03[19], ix04[19], ix05[19], ix06[19], ix07[19], ix08[19], ix09[19], ix10[19], ix11[19], ix12[19], ix13[19], ix14[19], ix15[19], ix16[19], ix17[19], ix18[19], ix19[19]};
      end
   end
endmodule

module PRBSGen15(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [14:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [14:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [14:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX15 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX15 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX15 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX15 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX15 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX15 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX15 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX15 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX15 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX15 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX15 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX15 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX15 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX15 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX15 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX15 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX15 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX15 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX15 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX15 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 15'b111111111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[14], ix01[14], ix02[14], ix03[14], ix04[14], ix05[14], ix06[14], ix07[14], ix08[14], ix09[14], ix10[14], ix11[14], ix12[14], ix13[14], ix14[14], ix15[14], ix16[14], ix17[14], ix18[14], ix19[14]};
      end
   end
endmodule

module PRBSGen11(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [10:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [10:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [10:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX11 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX11 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX11 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX11 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX11 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX11 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX11 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX11 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX11 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX11 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX11 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX11 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX11 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX11 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX11 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX11 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX11 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX11 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX11 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX11 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 11'b11111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[10], ix01[10], ix02[10], ix03[10], ix04[10], ix05[10], ix06[10], ix07[10], ix08[10], ix09[10], ix10[10], ix11[10], ix12[10], ix13[10], ix14[10], ix15[10], ix16[10], ix17[10], ix18[10], ix19[10]};
      end
   end
endmodule

module PRBSGen09(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [08:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [08:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [08:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX09 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX09 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX09 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX09 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX09 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX09 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX09 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX09 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX09 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX09 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX09 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX09 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX09 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX09 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX09 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX09 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX09 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX09 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX09 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX09 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 9'b111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[08], ix01[08], ix02[08], ix03[08], ix04[08], ix05[08], ix06[08], ix07[08], ix08[08], ix09[08], ix10[08], ix11[08], ix12[08], ix13[08], ix14[08], ix15[08], ix16[08], ix17[08], ix18[08], ix19[08]};
      end
   end
endmodule

module PRBSGen07(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [06:00]  poly_in;