patternlib.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

         data_out[03] <= prbs_data_out__pipe1[03] | ~(| history[16:03]);
         data_out[02] <= prbs_data_out__pipe1[02] | ~(| history[15:02]);
         data_out[01] <= prbs_data_out__pipe1[01] | ~(| history[14:01]);
         data_out[00] <= prbs_data_out__pipe1[00] | ~(| history[13:00]);
      end
   end
   
   PRBSGen20 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(prbs_data_out__pipe0), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_ITU_T_O150_54 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.4
   //   :
   //   : Shifter Stages  :  20
   //   : Length          :  2^20 - 1 = 1,048,575 bits
   //   : Longest Sequence:  19 (non-inverted)
   //   : Poly            :  x^20 + x^3
   //   :
   //   : 0010 0000 0000 0000 0001
   //   :    2    0    0    0    1
   //-------------------------------------------------------------------------
   parameter      POLY       = 20'h20001;
   parameter      MAX_LENGTH = 1'b0;
   
   PRBSGen20 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_out), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_ITU_T_O150_53 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.3
   //   :
   //   : Shifter Stages  :  15
   //   : Length          :  2^15 - 1 = 32,767 bits
   //   : Longest Sequence:  15 (inverted)
   //   : Poly            :  x^15 + x^14
   //   :
   //   : 000 0000 0000 0011
   //   :   0    0    0    3
   //-------------------------------------------------------------------------
   parameter      POLY       = 15'h003;
   parameter      MAX_LENGTH = 1'b0;
   
   wire [19:00]   data_inverted;
   assign data_out = ~ data_inverted;

   PRBSGen15 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_inverted), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_ITU_T_O150_52 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.2
   //   :
   //   : Shifter Stages  :  11
   //   : Length          :  2^11 - 1 = 2047 bits
   //   : Longest Sequence:  10 (non-inverted)
   //   : Poly            :  x^11 + x^9
   //   :
   //   : 000 0000 0101
   //   :   0    0    5
   //-------------------------------------------------------------------------
   parameter      POLY       = 11'h005;
   parameter      MAX_LENGTH = 1'b0;
   
   PRBSGen11 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_out), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_ITU_T_O150_51 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.1
   //   :
   //   : Shifter Stages  :  9
   //   : Length          :  2^9 - 1 = 511 bits
   //   : Longest Sequence:  8 (non-inverted)
   //   : Poly            :  x^9 + x^5
   //   :
   //   : 0 0001 0001
   //   : 0    1    1
   //-------------------------------------------------------------------------
   parameter      POLY       = 09'h011;
   parameter      MAX_LENGTH = 1'b0;
   
   PRBSGen09 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_out), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_7BIT (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // 7-bit Low Stress Pattern (not spec'd)
   //   :
   //   : Shifter Stages  :  7
   //   : Length          :  2^7 - 1 = 127 bits
   //   : Longest Sequence:  5 (non-inverted)
   //   : Poly            :  x^7 + x^6
   //   :
   //   : 000 0011
   //   :   0    3
   //-------------------------------------------------------------------------
   parameter      POLY       = 07'h03;
   parameter      MAX_LENGTH = 1'b0;
   
   PRBSGen07 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_out), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

//----------------------------------------------------------------
//
// II. PRBS Generator Section.
//   A. Contents:
//     1. PRBSGen32: 32-bit implementation
//     2. PRBSGen31: 31-bit implementation
//     3. PRBSGen29: 29-bit implementation
//     4. PRBSGen23: 23-bit implementation
//     5. PRBSGen20: 20-bit implementation
//     6. PRBSGen15: 15-bit implementation
//     7. PRBSGen11: 11-bit implementation
//     8. PRBSGen09:  9-bit implementation
//     9. PRBSGen07:  7-bit implementation
//
//   B. Port Summary.
//
//     data_out[19:00] (synchronous: clock_in)
//        Pattern data.
//
//     advance_in (synchronous: clock_in)
//        Enable pin for the pattern generators.  data_out will
//        update every cycle this pin is held high.
//
//     poly_in[XX:00] (synchronous: clock_in)
//        Number representing the LFSR's polynomial.
//
//     length_in (synchronous: clock_in)
//        High if the LFSR should be maximal length.
//
//     reset_in (synchronous: clock_in)
//        Synchronous reset. 
//
//     clock_in (clock: buffered)
//        Pattern clock.
//
//----------------------------------------------------------------
module PRBSGen32(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [31:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [31:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [31:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX32 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX32 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX32 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX32 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX32 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX32 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX32 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX32 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX32 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX32 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX32 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX32 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX32 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX32 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX32 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX32 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX32 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX32 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX32 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX32 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 32'b11111111111111111111111111111111;
         data_out <= 1;
      end else if (advance_in) begin
         PRBS <= ix19;
         data_out <= {ix00[31], ix01[31], ix02[31], ix03[31], ix04[31], ix05[31], ix06[31], ix07[31], ix08[31], ix09[31], ix10[31], ix11[31], ix12[31], ix13[31], ix14[31], ix15[31], ix16[31], ix17[31], ix18[31], ix19[31]};
      end
   end
endmodule

module PRBSGen31(data_out, advance_in, reset_in,
                 poly_in, length_in, clock_in
                 );

   output [19:00] data_out;
   input [30:00]  poly_in;
   input          length_in, advance_in, reset_in, clock_in;
   
   reg [30:00]    PRBS;
   reg [19:00]    data_out;
   
   wire [30:00]   ix00, ix01, ix02, ix03, ix04, ix05, ix06, ix07, ix08, ix09, ix10, ix11, ix12, ix13, ix14, ix15, ix16, ix17, ix18, ix19;

   IX31 intermediate_expression00(ix00, PRBS, poly_in, length_in);
   IX31 intermediate_expression01(ix01, ix00, poly_in, length_in);
   IX31 intermediate_expression02(ix02, ix01, poly_in, length_in);
   IX31 intermediate_expression03(ix03, ix02, poly_in, length_in);
   IX31 intermediate_expression04(ix04, ix03, poly_in, length_in);
   IX31 intermediate_expression05(ix05, ix04, poly_in, length_in);
   IX31 intermediate_expression06(ix06, ix05, poly_in, length_in);
   IX31 intermediate_expression07(ix07, ix06, poly_in, length_in);
   IX31 intermediate_expression08(ix08, ix07, poly_in, length_in);
   IX31 intermediate_expression09(ix09, ix08, poly_in, length_in);
   IX31 intermediate_expression10(ix10, ix09, poly_in, length_in);
   IX31 intermediate_expression11(ix11, ix10, poly_in, length_in);
   IX31 intermediate_expression12(ix12, ix11, poly_in, length_in);
   IX31 intermediate_expression13(ix13, ix12, poly_in, length_in);
   IX31 intermediate_expression14(ix14, ix13, poly_in, length_in);
   IX31 intermediate_expression15(ix15, ix14, poly_in, length_in);
   IX31 intermediate_expression16(ix16, ix15, poly_in, length_in);
   IX31 intermediate_expression17(ix17, ix16, poly_in, length_in);
   IX31 intermediate_expression18(ix18, ix17, poly_in, length_in);
   IX31 intermediate_expression19(ix19, ix18, poly_in, length_in);

   always @ (posedge clock_in) begin
      if (reset_in) begin 
         PRBS <= 31'b1111111111111111111111111111111;