patternlib.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  PatternLib.v
//      Version:  2.2  
//         Date:  05/14/03
//        Model:  Library of test bit-patterns.
//
//      Company:  Xilinx, Inc.
//  Contributor:  Mike Matera
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////
//
// Summary:
//
//   This file contains many modlues.  It is broken up into
// three sections:
//
// I. Polynomial Implementation Section.
//      This section contains modules that implement specific
//      PRBS polynomials and any thing else that must be done,
//      such as data inversion.
//
// II. PRBS Generator Section.
//      This section contains generalized modules for creating
//      n-bit PRBS patterns.  Each module in this section may
//      implement any polynomial (maximal length or not).
//
// III. Intermediate Expression Section.
//      The intermediate expression (IX) modules are used to
//      generate the cascaded logic required to generate 20-bit
//      remainders every clock cycle.
//
// Constant Summary:
//
// NOTE: As of version 1.4 file allows the option of compiling
//       Type1 or Type2 LFSRs using compile time flags.  The
//       following flags are MUTUALY EXCLUSIVE (define only one).
//
// WITH_TYPE1
//   Defined to instantiate Type1 LFSRs.
//
// WITH_TYPE2
//   Defined to instantiate Type1 LFSRs.
//
// PatternLib.v,v 1.9 2003/03/24 23:22:24 matera
//----------------------------------------------------------------
`ifdef PATTERNLIB `else 
`define PATTERNLIB

`timescale               100ps/10ps 

//----------------------------------------------------------------
//
// I. Polynomial Implementation Section.
//   A. Contents
//     1. PRBS_32BIT   : Non Standard 32-bit PRBS.
//     2. ITU_T_O150_51: ITU-T Recomendation O.150 section 5.1.
//     3. ITU_T_O150_52: ITU-T Recomendation O.150 section 5.2.
//     4. ITU_T_O150_53: ITU-T Recomendation O.150 section 5.3.
//     5. ITU_T_O150_54: ITU-T Recomendation O.150 section 5.4.
//     6. ITU_T_O150_55: ITU-T Recomendation O.150 section 5.5.
//     7. ITU_T_O150_56: ITU-T Recomendation O.150 section 5.6.
//     8. ITU_T_O150_57: ITU-T Recomendation O.150 section 5.7.
//     9. ITU_T_O150_58: ITU-T Recomendation O.150 section 5.8.
//    10. PRBS_7BIT    : Non Standard 7-bit PRBS.
//
//   B. Port Summary.
//
//     data_out[19:00] (synchronous: clock_in)
//        Pattern data.
//
//     advance_in (synchronous: clock_in)
//        Enable pin for the pattern generators.  data_out will
//        update every cycle this pin is held high.
//
//     reset_in (synchronous: clock_in)
//        Synchronous reset. 
//
//     clock_in (clock: buffered)
//        Pattern clock.
//
//----------------------------------------------------------------

module PRBS_32BIT (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // 32-bit Pattern (not specd)
   //   :
   //   : Shifter Stages  :  32
   //   : Length          :  2^31 - 1 = 4G bits
   //   : Longest Sequence:  32 (not-inverted)
   //   : Poly            :  x^32 + x^31 + x^30 + x^10
   //   :
   //   : 0000 0000 0100 0000 0000 0000 0000 0111
   //   :    0    0    4    0    0    0    0    7
   //-------------------------------------------------------------------------
   parameter      POLY       = 32'h00400007;
   parameter      MAX_LENGTH = 1'b0;
   
   PRBSGen32 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_out), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );
   
endmodule

module PRBS_ITU_T_O150_58 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.8
   //   :
   //   : Shifter Stages  :  31
   //   : Length          :  2^31 - 1 = 2,147,483,647 bits
   //   : Longest Sequence:  31 (inverted)
   //   : Poly            :  x^31 + x^28
   //   :
   //   : 000 0000 0000 0000 0000 0000 0000 1001
   //   :   0    0    0    0    0    0    0    9
   //-------------------------------------------------------------------------
   parameter      POLY       = 31'h00000009;
   parameter      MAX_LENGTH = 1'b0;
   
   wire [19:00]   data_inverted;
   assign data_out = ~ data_inverted;

   PRBSGen31 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_inverted), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );
   
endmodule

module PRBS_ITU_T_O150_57 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.7
   //   :
   //   : Shifter Stages  :  29
   //   : Length          :  2^29 - 1 = 536,870,911 bits
   //   : Longest Sequence:  29 (inverted)
   //   : Poly            :  x^29 + x^27
   //   :
   //   : 0 0000 0000 0000 0000 0000 0000 0101
   //   : 0    0    0    0    0    0    0    5
   //-------------------------------------------------------------------------
   parameter      POLY       = 29'h00000005;
   parameter      MAX_LENGTH = 1'b0;
   
   wire [19:00]   data_inverted;
   assign data_out = ~ data_inverted;

   PRBSGen29 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_inverted), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );
   
endmodule

module PRBS_ITU_T_O150_56 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.6
   //   :
   //   : Shifter Stages  :  23
   //   : Length          :  2^23 - 1 = 8,388,607 bits
   //   : Longest Sequence:  23 (inverted)
   //   : Poly            :  x^23 + x^18
   //   :
   //   : 000 0000 0000 0000 0010 0001
   //   :   0    0    0    0    2    1
   //-------------------------------------------------------------------------
   parameter      POLY       = 23'h000021;
   parameter      MAX_LENGTH = 1'b0;
   
   wire [19:00]   data_inverted;
   assign data_out = ~ data_inverted;

   PRBSGen23 prbs 
      (
       .poly_in(POLY), .length_in(MAX_LENGTH), 
       .data_out(data_inverted), 
       .advance_in(advance_in), 
       .reset_in(reset_in),
       .clock_in(clock_in)
       );

endmodule

module PRBS_ITU_T_O150_55 (data_out, advance_in, reset_in, clock_in);
   output [19:00] data_out;
   input          advance_in, reset_in, clock_in;
   
   //-------------------------------------------------------------------------
   // ITU-T Recommendation O.150 Section 5.5
   //   :
   //   : Shifter Stages  :  20
   //   : Length          :  2^20 - 1 = 1,048,575 bits
   //   : Longest Sequence:  14 (special sequence)
   //   : Poly            :  x^20 + x^17
   //   : NOTE            :  This pattern uses zeros suppression.
   //   :
   //   : 0000 0000 0000 0000 1001
   //   :    0    0    0    0    9
   //-------------------------------------------------------------------------
   parameter      POLY       = 20'h00009;
   parameter      MAX_LENGTH = 1'b0;

   //
   // Zeros suppression:
   //
   reg [19:00]    prbs_data_out__pipe1, data_out; 
   wire [19:00]   prbs_data_out__pipe0;

   wire [32:00]   history = {prbs_data_out__pipe1[18:00], prbs_data_out__pipe0[19:06]};

   always @ (posedge clock_in) begin
      if (reset_in) begin
         prbs_data_out__pipe1 <= 20'b1;
      end else if (advance_in) begin
         prbs_data_out__pipe1 <= prbs_data_out__pipe0;
      end
   end

   always @ (posedge clock_in) begin
      if (reset_in) begin
         data_out <= 20'b1;
      end else if (advance_in) begin
         data_out[19] <= prbs_data_out__pipe1[19] | ~(| history[32:19]);
         data_out[18] <= prbs_data_out__pipe1[18] | ~(| history[31:18]);
         data_out[17] <= prbs_data_out__pipe1[17] | ~(| history[30:17]);
         data_out[16] <= prbs_data_out__pipe1[16] | ~(| history[29:16]);
         data_out[15] <= prbs_data_out__pipe1[15] | ~(| history[28:15]);
         data_out[14] <= prbs_data_out__pipe1[14] | ~(| history[27:14]);
         data_out[13] <= prbs_data_out__pipe1[13] | ~(| history[26:13]);
         data_out[12] <= prbs_data_out__pipe1[12] | ~(| history[25:12]);
         data_out[11] <= prbs_data_out__pipe1[11] | ~(| history[24:11]);
         data_out[10] <= prbs_data_out__pipe1[10] | ~(| history[23:10]);
         data_out[09] <= prbs_data_out__pipe1[09] | ~(| history[22:09]);
         data_out[08] <= prbs_data_out__pipe1[08] | ~(| history[21:08]);
         data_out[07] <= prbs_data_out__pipe1[07] | ~(| history[20:07]);
         data_out[06] <= prbs_data_out__pipe1[06] | ~(| history[19:06]);
         data_out[05] <= prbs_data_out__pipe1[05] | ~(| history[18:05]);
         data_out[04] <= prbs_data_out__pipe1[04] | ~(| history[17:04]);