gigabitber_tx.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  GigabitBER_TX.v
//      Version:  2.2
//         Date:  05/14/03
//        Model:  Transmitter Core for the Bit Error Rate Tester.
//                GigabitBER_TX sends a pseudo random bit stream for the
//                purposes of determining a Bit Error Rate.  After reset the
//                transmitter sends a long string of commas in order to
//                assist in initializing the receiver and align the link.
//
//      Company:  Xilinx, Inc.
//  Contributor:  Mike Matera
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////

`ifdef GIGABITBER_TX `else 
`define GIGABITBER_TX

`timescale               100ps/10ps 

//-------------------------------------------------------------
// 
// Constant Summary:
//
// COMMA: 
//  The value to send as the comma word.
//
// TX_INIT_COUNTER_MSB: 
//  Number of bits in the init_wait counter.  This controls
//  the number of cycles to send a comma before starting
//  the PRBS.
//
//-------------------------------------------------------------

module GigabitBER_TX(data_out, error_insert_pulse, pattern_select_in, reset_in,
                     clock_in);

   //-------------------------------------------------------------
   // 
   // Port Summary:
   // 
   // data_out[19:00] (synchronous: clock_in)
   //    Data to the MGT.
   //
   // pattern_select_in[03:00] (synchronous: clock_in)
   //    Selects which PRBS Pattern to use.
   //
   // reset_in (synchronous: clock_in)
   //    Resets the transmitter. 
   //
   // clock_in (clock: buffered)
   //    Transmitter clock.  This clock must also be connected to
   //    TXUSRCLK on the MGT.
   //
   //-------------------------------------------------------------

   output [19:00] data_out;
   input [03:00]  pattern_select_in;
   input          reset_in, clock_in;
   input          error_insert_pulse;


   parameter      RESET_STATE   = 3'b001,
                  INIT_STATE    = 3'b010,
                  SENDING_STATE = 3'b100;
         
   reg [`TX_INIT_COUNTER_MSB:00] InitWait, InitWait__next;
   reg [02:00]                   MachineState, MachineState__next;
   reg [19:00]                   data_out, data_out__next;
   
   wire                          sending_bit, init_bit, reset_bit;
   assign                        {sending_bit, init_bit, reset_bit} = MachineState;
   
   wire [19:00]                  PRBSData;
   
   PatternGenerator prbs_comp 
     (
      .data_pipe0a_out(/*Not Used*/),
      .data_pipe0b_out(/*Not Used*/),
      .data_pipe1_out(PRBSData),
      .error_insert_pulse(error_insert_pulse),
      .pattern_select_in(pattern_select_in),
      .advance_in(sending_bit), .reset_in(reset_bit),
      .clock_in(clock_in)
      );
   
   always @ (MachineState or PRBSData) begin
      case (MachineState)       
        RESET_STATE:    data_out__next <= `COMMA;
        INIT_STATE:     data_out__next <= `COMMA;
        SENDING_STATE:  data_out__next <= PRBSData;
        default:        data_out__next <= `COMMA;
      endcase
   end
   
   always @ (MachineState or InitWait) begin
      MachineState__next <= MachineState;
      InitWait__next <= InitWait;
                        
      case (MachineState)
        RESET_STATE:    MachineState__next <= INIT_STATE;      
        INIT_STATE:  
                        begin
                           InitWait__next <= InitWait + 1;
                           if (InitWait[`TX_INIT_COUNTER_MSB]) MachineState__next <= SENDING_STATE;
                           else MachineState__next <= INIT_STATE;
                        end
        SENDING_STATE:  MachineState__next <= SENDING_STATE;
        default:        MachineState__next <= RESET_STATE;
      endcase
   end
   
   always @ (posedge clock_in) begin
      if (reset_in) begin
         MachineState <= RESET_STATE;
         InitWait <= 0;
         data_out <= 0;
      end else begin
         MachineState <= MachineState__next;
         InitWait <= InitWait__next;
         data_out <= data_out__next;
      end
   end   
endmodule

`endif