mgtboardbert.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

    
      assign bref_clock_in_bot = 1'b0;
      assign bref2_clock_in_bot = 1'b0; 
      
    `endif

  `endif


 `ifdef USER_USE_TOP_BOT_GT_yes
   assign bref_clock_in_i_0 = bref_clock_in;
   assign bref2_clock_in_i_0 = bref2_clock_in;
   assign bref_clock_in_i_1 = bref_clock_in_bot;
   assign bref2_clock_in_i_1 = bref2_clock_in_bot;
   assign ClockSelect_0 = ClockSelect;
   assign ClockSelect_1 = ~ClockSelect;
   assign MGTClock_0 = MGTClock;
   assign MGTClock_1 = MGTClock_bot;
   assign MGTReset_0 = MGTReset;
   assign MGTReset_1 = MGTReset_bot;
`else
   assign bref_clock_in_i_0 = bref_clock_in;
   assign bref2_clock_in_i_0 = bref2_clock_in;
   assign bref_clock_in_i_1 = bref_clock_in;
   assign bref2_clock_in_i_1 = bref2_clock_in;
   assign ClockSelect_0 = ClockSelect;
   assign ClockSelect_1 = ClockSelect;
   assign MGTClock_0 = MGTClock;
   assign MGTClock_1 = MGTClock;
   assign MGTReset_0 = MGTReset;
   assign MGTReset_1 = MGTReset;
 `endif


 // HID Control Signals:
 assign MasterReset   = Push_buttons_in[0]; // & Push_buttons_in;


`ifdef XBERT_FOR_SIM_ONLY  // for simulation

   assign TXInhibit  = { DIP_switch_in[8],  DIP_switch_in[0]};
   assign MGTPowerDown = { DIP_switch_in[9],  DIP_switch_in[1]};
   assign LoopbackMode = { DIP_switch_in[11:10],  DIP_switch_in[3:2]};
   assign ErrorInsert =   DIP_switch_in[14:13];
   assign PatternSelect1 = DIP_switch_in[07:04];
   assign PatternSelect2 = DIP_switch_in[19:16];
   assign ClockSelect = DIP_switch_in[15];
   assign IdleMGTPowerDown  = DIP_switch_in[21:20];// 0 : Active
   assign IdleTXInhibit  = { DIP_switch_in[23],  DIP_switch_in[22]};
   assign IdleLoopbackMode = { DIP_switch_in[27:26],  DIP_switch_in[25:24]};
   assign ProgDelay =  DIP_switch_in[31:28];

   assign LEDs_out = LEDs;

   LevelDetect tx_reset0 (.sig_level_out(BERTReset[0]), .sig_in(Push_buttons_in[1]), .clock_in(MGTClock_0));
   LevelDetect tx_reset1 (.sig_level_out(BERTReset[2]), .sig_in(Push_buttons_in[2]), .clock_in(MGTClock_1));
   LevelDetect rx_reset0  (.sig_level_out(BERTReset[1]), .sig_in(Push_buttons_in[3]), .clock_in(RECClock_buffered[0]));
   LevelDetect rx_reset1  (.sig_level_out(BERTReset[3]), .sig_in(Push_buttons_in[3]), .clock_in(RECClock_buffered[1]));

`else // for hardware implementation

   assign TXInhibit  = { DIPSwitches[8],  DIPSwitches[0]};
   assign MGTPowerDown = { DIPSwitches[9],  DIPSwitches[1]};
   assign LoopbackMode = { DIPSwitches[11:10],  DIPSwitches[3:2]};
   assign ErrorInsert =   DIPSwitches[14:13];
   assign PatternSelect1 = DIPSwitches[07:04];
   assign PatternSelect2 = DIPSwitches[19:16];
   assign ClockSelect = DIPSwitches[15];
   assign IdleMGTPowerDown = DIPSwitches[21:20];// 0 : Active
   assign IdleTXInhibit  = { DIPSwitches[23],  DIPSwitches[22]};
   assign IdleLoopbackMode = { DIPSwitches[27:26],  DIPSwitches[25:24]};
   assign ProgDelay =  DIPSwitches[31:28];

   assign LEDs_out = LEDs_pwm;

   LevelDetect tx_reset0 (.sig_level_out(BERTReset[0]), .sig_in(PushButtons[1]), .clock_in(MGTClock_0));
   LevelDetect tx_reset1 (.sig_level_out(BERTReset[2]), .sig_in(PushButtons[2]), .clock_in(MGTClock_1));
   LevelDetect rx_reset0  (.sig_level_out(BERTReset[1]), .sig_in(PushButtons[3]), .clock_in(RECClock_buffered[0]));
   LevelDetect rx_reset1  (.sig_level_out(BERTReset[3]), .sig_in(PushButtons[3]), .clock_in(RECClock_buffered[1]));

`endif //XBERT_FOR_SIM_ONLY



   assign LEDs[00] = MGTClock_ok_0 ? link_r[0] : 1'b0;
   assign LEDs[01] = TXDetect[0];
   assign LEDs[02] = MGTClock_ok_0 ? data_detect_r[0] : 1'b0;
   assign LEDs[03] = Error[0];
   assign LEDs[04] = abort_r[0];
   assign LEDs[05] = | dropped_frames_0;
   assign LEDs[06] = TXInhibit[0];
   assign LEDs[07] = MGTPowerDown[0];

   assign LEDs[08] = MGTClock_ok_1 ? link_r[1] : 1'b0;
   assign LEDs[09] = TXDetect[1];
   assign LEDs[10] = MGTClock_ok_1 ? data_detect_r[1] : 1'b0;
   assign LEDs[11] = Error[1];
   assign LEDs[12] = abort_r[1];
   assign LEDs[13] = | dropped_frames_1;
   assign LEDs[14] = TXInhibit[1];
   assign LEDs[15] = MGTPowerDown[1];

   assign recovered_clocks_out[1:0] = RECClock[1:0];    // rx recovered clock sent to an external pin for testing purpose


   FDDRCPE DDR_BREF_CLK( // send back the clock to an external pin for testing purpose
     .Q(recovered_clocks_out[2]),
     .C0(MGTClock),
     .C1(~MGTClock),
     .CE(1'b1),
     .CLR(1'b0),
     .D0(1'b1),
     .D1(1'b0),
     .PRE(1'b0)
   );

   assign dropped_frames_out       = {7'b0, dropped_frames_1[24:0], 7'b0, dropped_frames_0[24:0]};
   assign total_frames_out         = {total_frames_1[47:0], total_frames_0[47:0]}; 
   assign error_factor_out         = {error_factor_1[39:0], error_factor_0[39:0]};    

   //MGT REF Clock detection
   FDCP MGTClock_Detect_FDP_0_a(.Q(MGTClock_ok_0_i), .C(MGTClock_0), .PRE (1'b0), .CLR(MasterReset), .D(1'b1));
   FDCP MGTClock_Detect_FDP_1_a(.Q(MGTClock_ok_1_i), .C(MGTClock_1), .PRE (1'b0), .CLR(MasterReset), .D(1'b1));
   FDCP MGTClock_Detect_FDP_0_b(.Q(MGTClock_ok_0), .C(MGTClock_0), .PRE (1'b0), .CLR(MasterReset), .D(MGTClock_ok_0_i));
   FDCP MGTClock_Detect_FDP_1_b(.Q(MGTClock_ok_1), .C(MGTClock_1), .PRE (1'b0), .CLR(MasterReset), .D(MGTClock_ok_1_i));


   always@(posedge MGTClock_0)
    begin
              link_r[0]        <= Link[0];
              abort_r[0]       <= Abort[0];
              data_detect_r[0] <= DataDetect[0];
    end

   always@(posedge MGTClock_1)
    begin
              link_r[1]        <= Link[1];
              abort_r[1]       <= Abort[1];
              data_detect_r[1] <= DataDetect[1];
    end

   assign    status[7:0] = MGTClock_ok_0 ? {TXInhibit[0],MGTPowerDown[0], LoopbackMode[1:0],link_r[0], abort_r[0],TXDetect[0], data_detect_r[0]} : 8'b0;
   assign    status[15:8] = MGTClock_ok_1 ? {TXInhibit[1],MGTPowerDown[1], LoopbackMode[3:2],link_r[1], abort_r[1],TXDetect[1], data_detect_r[1]} : 8'b0;
   assign    status[16]   = MGTClock_ok_0 ? overflow_flag_0 : 1'b0;
   assign    status[17]   = MGTClock_ok_1 ? overflow_flag_1 : 1'b0;
   assign    status[20:18] = bert_config_code;
   assign    status[24:21] = MGTClock_ok_0 ? {IdleTXInhibit[0],IdleMGTPowerDown[0],IdleLoopbackMode[1:0]} : 4'b0;
   assign    status[28:25] = MGTClock_ok_1 ? {IdleTXInhibit[1],IdleMGTPowerDown[1],IdleLoopbackMode[3:2]} : 4'b0;
   

   VirtexIIpMGTBoardInterface iface_comp
     (
      .clock_rt_in(rt_clock_in),

      .clock_direct1_in(bref2_clock_in),
      .clock_direct0_in(bref_clock_in),
      .clock_select_in(ClockSelect),

      .clock_direct1_in_bot(bref2_clock_in_bot),
      .clock_direct0_in_bot(bref_clock_in_bot),
      .clock_select_in_bot(~ClockSelect),

      .mgt_clock_out(MGTClock),.mgt_clock_out_bot(MGTClock_bot),
      .mgt_reset_out(MGTReset),
      .mgt_reset_out_bot(MGTReset_bot),
      .pwm_locked_out(PWMLocked),

      .LEDs_in(LEDs), .LEDs_out(LEDs_pwm),
      .DIPs_in(DIP_switch_in), .DIPs_out(DIPSwitches),
      .push_buttons_in(Push_buttons_in), .push_buttons_out(PushButtons),
      .human_update_out(HumanEvent),

      .system_reset_in(MasterReset)
      );


   VirtexIIpBERT bert0_comp
     (
       .loopback_mode_in(LoopbackMode[1:0]),
       .idleloopback_mode_in(IdleLoopbackMode[1:0]),
       .tx_inhibit_in(TXInhibit[0]), .powerdown_in(MGTPowerDown[0] | MGTReset_0),
       .idletx_inhibit_in(IdleTXInhibit[0]), .idlepowerdown_in(IdleMGTPowerDown[0] | MGTReset_0),

       .serial_n_out(serial_n_out[0]), .serial_p_out(serial_p_out[0]),
       .serial_n_out_idle(serial_n_out_idle[0]), .serial_p_out_idle(serial_p_out_idle[0]),
       .serial_n_in(serial_n_in[0]), .serial_p_in(serial_p_in[0]),
       .serial_n_in_idle(serial_n_in_idle[0]), .serial_p_in_idle(serial_p_in_idle[0]),

       .total_frames_out(total_frames_0),
       .error_figure_out(error_factor_0),
       .dropped_frames_out(dropped_frames_0),

       .bec_count_out(bec_count_out_0),
       .overflow_flag(overflow_flag_0),
       .error_insert(ErrorInsert[0]),

       .link_out(Link[0]), .error_out(Error[0]), .abort_out(Abort[0]),
       .tx_detect_out(TXDetect[0]), .data_detect_out(DataDetect[0]),

       .pattern_select_in(PatternSelect1),
       .control_icon(control0_icon),
       .ProgDelay(ProgDelay),

       .tx_reset_in(BERTReset[0]), .rx_reset_in(BERTReset[1] | MGTPowerDown[0]),
       .mgt_tx_reset_in(MGTReset_0), .mgt_rx_reset_in(MGTReset_0),

       .clock_direct0_in(bref_clock_in_i_0), .clock_direct1_in(bref2_clock_in_i_0),
       .clock_select_in(ClockSelect_0),

       .clock_buffered_in(MGTClock_0),
       .RECClock_buffered(RECClock_buffered[0]),

       .recovered_clock_out(RECClock[0]),
       .data_to_chipscope (data_to_chipscope_0)
       );

   VirtexIIpBERT bert1_comp
     (
       .loopback_mode_in(LoopbackMode[3:2]),
       .idleloopback_mode_in(IdleLoopbackMode[3:2]),
       .tx_inhibit_in(TXInhibit[1]), .powerdown_in(MGTPowerDown[1] | MGTReset_1),
       .idletx_inhibit_in(IdleTXInhibit[1]), .idlepowerdown_in(IdleMGTPowerDown[1] | MGTReset_1),

       .serial_n_out(serial_n_out[1]), .serial_p_out(serial_p_out[1]),
       .serial_n_out_idle(serial_n_out_idle[1]), .serial_p_out_idle(serial_p_out_idle[1]),
       .serial_n_in(serial_n_in[1]), .serial_p_in(serial_p_in[1]),
       .serial_n_in_idle(serial_n_in_idle[1]), .serial_p_in_idle(serial_p_in_idle[1]),

       .total_frames_out(total_frames_1),
       .error_figure_out(error_factor_1),
       .dropped_frames_out(dropped_frames_1),

       .bec_count_out(bec_count_out_1),
       .overflow_flag(overflow_flag_1),
       .error_insert(ErrorInsert[1]),

       .link_out(Link[1]), .error_out(Error[1]), .abort_out(Abort[1]),
       .tx_detect_out(TXDetect[1]), .data_detect_out(DataDetect[1]),

       .pattern_select_in(PatternSelect2),
       .control_icon(control1_icon),
       .ProgDelay(ProgDelay),

       .tx_reset_in(BERTReset[2]), .rx_reset_in(BERTReset[3] | MGTPowerDown[1]),
       .mgt_tx_reset_in(MGTReset_1), .mgt_rx_reset_in(MGTReset_1),

       .clock_direct0_in(bref_clock_in_i_1), .clock_direct1_in(bref2_clock_in_i_1),
       .clock_select_in(ClockSelect_1),

       .clock_buffered_in(MGTClock_1),
       .RECClock_buffered(RECClock_buffered[1]),

       .recovered_clock_out(RECClock[1]),
       .data_to_chipscope (data_to_chipscope_1)
       );

    //3-bit Configuration Register
    FDE configreg0(
         .D(bert_config_code[0]),
         .CE(1'b0),
         .C(rt_clock_in),
         .Q(bert_config_code[0]));

    FDE configreg1(
         .D(bert_config_code[1]),
         .CE(1'b0),
         .C(rt_clock_in),
         .Q(bert_config_code[1]));

    FDE configreg2(
         .D(bert_config_code[2]),
         .CE(1'b0),
         .C(rt_clock_in),
         .Q(bert_config_code[2]));


    /////////////////////////////////////////////////
    // Optional ILA Core
    /////////////////////////////////////////////////

   `ifdef USE_ILA_0
   
     ila i_ila
     (
      .control(control0_icon),
      .clk(RECClock_buffered[0]),
      .data(data_to_chipscope_0),
      .trig0(data_to_chipscope_0[0])
     );

     icon i_icon
     ( .control0(control0_icon)  );
     
   `else

           `ifdef USE_ILA_1


             ila i_ila
             (
              .control(control0_icon),
              .clk(RECClock_buffered[1]),
              .data(data_to_chipscope_1),
              .trig0(data_to_chipscope_1[0])
             );
             
             icon i_icon
             ( .control0(control0_icon)  );
             
            `endif     
     
   `endif


endmodule

`endif