mgt_bert_4.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  VirtexIIpBERT.v
//      Version:  2.2
//         Date:  05/14/03
//        Model:  Implementation of the MGT for BERT testing.
//
//      Company:  Xilinx, Inc.
//  Contributor:  Mike Matera
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////

// Summary: MGT_BERT_4 is an adapter for the raw GT module
//   for the convinience of outer modules implementing a
//   parallel bit error rate test.  The functionality of the
//   GT is partly sacrificed for the benefit of testing.
//

`ifdef MGT_BERT_4 `else
`define MGT_BERT_4

module MGT_BERT_4(
                  // MGT Clocks:
                  ref_clock0_in, ref_clock1_in,
                  ref_clock_select_in,

                  tx_clock_in, rx_clock_in, rec_clock_out,

                  // MGT Parallel Data:
                  tx_parallel_data_in, rx_parallel_data_out,

                  // MGT Serial Data:
                  serial_n_out, serial_p_out,
                  serial_n_in, serial_p_in,

                  // MGT Control Signals (TX Domain):
                  loopback_mode_in, tx_reset_in, tx_inhibit_in,

                  // MGT Control Signals (RX Domain):
                  rx_reset_in, rx_comma_detect_out, rx_realign_out,

                  // MGT Control Signals (Asynchronous):
                  powerdown_in, en_p_comma_align_in
                  );

   //-------------------------------------------------------------
   //
   // Port Summary:
   //
   // ref_clock0_in (clock: unfuffered)
   //    One of the reference clocks for the GT:  Must come directly from IO.
   //
   // ref_clock1_in (clock: unfuffered)
   //    One of the reference clocks for the GT:  Must come directly from IO.
   //
   // ref_clock_select_in (asynchronous)
   //    Selectes which reference clock to use.
   //    0: use ref_clock0_in
   //    1: use ref_clock1_in.
   //
   // tx_clock_in (clock: buffered)
   //    Clock for the digital TX portion of the GT.
   //
   // rx_clock_in (clock: buffered)
   //    Clock for the digital RX portion of the GT.
   //
   // rec_clock_out (clock: unbuffered (output))
   //    Unbuffered version of the recovered clock.
   //
   // tx_parallel_data_in[19:00] (synchronous: tx_clock_in)
   //    Parallel input data to the GT.
   //
   // rx_parallel_data_out[19:00] (synchronous: rx_clock_in)
   //    Parallel output data from the GT.
   //
   // rx_comma_detect_out (synchronous: rx_clock_in)
   //    High when the PMA detects the selected COMMA.
   //
   // rx_realign_out (synchronous: rx_clock_in)
   //    High when the PCS is realigning the RX buffer due
   //    to the recipt of a selected COMMA.
   //
   // serial_n_out
   // serial_p_out (analog)
   //    Must be connected to dedicated GT TX pads.
   //
   // serial_n_in
   // serial_p_in (analog)
   //    Must be connected to dedicated GT RX pads.
   //
   // loopback_mode_in[01:00] (synchronous: tx_clock_in)
   //    Value of the GTs loopback mode input.
   //
   // tx_reset_in (synchronous: tx_clock_in)
   //    Synchronous reset for the TX portion of the GT.
   //
   // tx_inhibit_in (synchronous: tx_clock_in)
   //    Prevents the GT from transmitting data.
   //
   // rx_reset_in (synchronous: rx_clock_in)
   //    Synchronous reset for the RX portion of the GT.
   //
   // powerdown_in (asynchronous)
   //    Puts the GT into powerdown mode.
   //
   // powerdown_in (asynchronous)
   //    Puts the GT into powerdown mode.
   //
   // en_m_comma_align_in (asynchronous)
   //    Allows the inverted comma to be detected.
   //
   // en_p_comma_align_in (asynchronous)
   //    Allows the true comma to be detected.
   //
   //-------------------------------------------------------------

   // MGT Parallel Data:
   output [19:00] rx_parallel_data_out;
   input [19:00]  tx_parallel_data_in;
   // MGT Clocks:
   input          ref_clock0_in, ref_clock1_in,
                  ref_clock_select_in, tx_clock_in, rx_clock_in;
   output         rec_clock_out;
   // MGT Serial Data:
   output         serial_n_out, serial_p_out;
   input          serial_n_in, serial_p_in;
   // MGT Control Signals (TX Domain):
   input [01:00]  loopback_mode_in;
   input          tx_reset_in, tx_inhibit_in;
   // MGT Control Signals (RX Domain):
   input          rx_reset_in;
   output         rx_comma_detect_out, rx_realign_out;

   // MGT Control Signals (Asynchronous):
   input          powerdown_in, en_p_comma_align_in;

   // Control Signals:
   wire [01:00] LOOPBACK          = loopback_mode_in;
   wire         TXINHIBIT         = tx_inhibit_in;
   wire [03:00] TXBYPASS8B10B     = 4'b1111;
   wire [03:00] TXCHARISK         = 4'b0000;
   wire         ENPCOMMAALIGN     = en_p_comma_align_in;
   wire         RXCOMMADET;
   wire         RXREALIGN;

   // High Speed Serial:
   wire         TXN;
   wire         TXP;
   wire         RXN               = serial_n_in;
   wire         RXP               = serial_p_in;

   // Resets:
   wire         POWERDOWN         = powerdown_in;
   wire         TXRESET           = tx_reset_in;
   wire         RXRESET           = rx_reset_in;

   // Clocks:
   wire         REFCLK            = ref_clock0_in;
   wire         REFCLK2           = ref_clock1_in;
   wire         REFCLKSEL         = ref_clock_select_in;
   wire         TXUSRCLK          = tx_clock_in;
   wire         TXUSRCLK2         = tx_clock_in;
   wire         RXUSRCLK          = rx_clock_in;
   wire         RXUSRCLK2         = rx_clock_in;

   wire         RXRECCLK;

   // TX Data:
   wire [31:00] TXDATA;
   wire [03:00] TXCHARDISPMODE;
   wire [03:00] TXCHARDISPVAL;

   // RX Data:
   wire [31:00] RXDATA;
   wire [03:00] RXCHARISK;
   wire [03:00] RXRUNDISP;

   // Misc Signals:
   wire [19:00] RXDATA_WIDE = {RXCHARISK[1], RXRUNDISP[1], RXDATA[15:08],
                               RXCHARISK[0], RXRUNDISP[0], RXDATA[07:00]};
   wire [39:00] TXDATA_WIDE;
   assign {TXCHARDISPMODE[3], TXCHARDISPVAL[3], TXDATA[31:24],
           TXCHARDISPMODE[2], TXCHARDISPVAL[2], TXDATA[23:16],
           TXCHARDISPMODE[1], TXCHARDISPVAL[1], TXDATA[15:08],
           TXCHARDISPMODE[0], TXCHARDISPVAL[0], TXDATA[07:00]} = TXDATA_WIDE;
   assign TXDATA_WIDE[19:00] = tx_parallel_data_in;
   assign TXDATA_WIDE[39:20] = 20'b0;

   assign rx_parallel_data_out = RXDATA_WIDE[19:00];
   assign serial_n_out = TXN;
   assign serial_p_out = TXP;
   assign rx_comma_detect_out = RXCOMMADET;
   assign rx_realign_out = RXREALIGN;
   assign rec_clock_out = RXRECCLK;

 `ifdef XBERT_FOR_SIM_ONLY 


   GT_CUSTOM MGT (  // Xilinx 5.1i GT_CUSTOM cell model
        .ENMCOMMAALIGN          (1'b0),
        .ENPCOMMAALIGN          (ENPCOMMAALIGN),

        .CHBONDDONE             (),
        .CHBONDO                (),
        .CONFIGOUT              (),
        .RXBUFSTATUS            (),
        .RXCHARISCOMMA          (),
        .RXCHARISK              (RXCHARISK),
        .RXCHECKINGCRC          (),
        .RXCLKCORCNT            (),
        .RXCOMMADET             (RXCOMMADET),
        .RXCRCERR               (),
        .RXDATA                 (RXDATA),
        .RXDISPERR              (),
        .RXLOSSOFSYNC           (),
        .RXNOTINTABLE           (),
        .RXREALIGN              (RXREALIGN),
        .RXRECCLK               (RXRECCLK),
        .RXRUNDISP              (RXRUNDISP),
        .TXBUFERR               (),
        .TXKERR                 (),
        .TXN                    (TXN),
        .TXP                    (TXP),
        .TXRUNDISP              (),

        .CHBONDI                (4'b0),
        .CONFIGENABLE           (1'b0),
        .CONFIGIN               (1'b0),
        .ENCHANSYNC             (1'b0),
        .LOOPBACK               (LOOPBACK),
        .POWERDOWN              (POWERDOWN),
        .BREFCLK                (1'b0),
        .BREFCLK2               (1'b0),
        .REFCLK                 (REFCLK),   // Use REFCLK for simulation
        .REFCLK2                (REFCLK2),
        .REFCLKSEL              (REFCLKSEL),
        .RXN                    (RXN),
        .RXP                    (RXP),
        .RXPOLARITY             (1'b0),
        .RXRESET                (RXRESET),
        .RXUSRCLK               (RXUSRCLK),
        .RXUSRCLK2              (RXUSRCLK2),
        .TXBYPASS8B10B          (TXBYPASS8B10B),
        .TXCHARDISPMODE         (TXCHARDISPMODE),
        .TXCHARDISPVAL          (TXCHARDISPVAL),
        .TXCHARISK              (TXCHARISK),
        .TXDATA                 (TXDATA),
        .TXFORCECRCERR          (1'b0),
        .TXINHIBIT              (TXINHIBIT),
        .TXPOLARITY             (1'b0),
        .TXRESET                (TXRESET),
        .TXUSRCLK               (TXUSRCLK),
        .TXUSRCLK2              (TXUSRCLK2)
      );


`else  // load GT_* cell for implementation

   GT_CUSTOM MGT (   // Xilinx 5.1i GT_CUSTOM cell model
        .ENMCOMMAALIGN          (1'b0),
        .ENPCOMMAALIGN          (ENPCOMMAALIGN),

        .CHBONDDONE             (),
        .CHBONDO                (),
        .CONFIGOUT              (),
        .RXBUFSTATUS            (),
        .RXCHARISCOMMA          (),
        .RXCHARISK              (RXCHARISK),
        .RXCHECKINGCRC          (),
        .RXCLKCORCNT            (),
        .RXCOMMADET             (RXCOMMADET),
        .RXCRCERR               (),
        .RXDATA                 (RXDATA),
        .RXDISPERR              (),
        .RXLOSSOFSYNC           (),
        .RXNOTINTABLE           (),
        .RXREALIGN              (RXREALIGN),
        .RXRECCLK               (RXRECCLK),
        .RXRUNDISP              (RXRUNDISP),
        .TXBUFERR               (),
        .TXKERR                 (),
        .TXN                    (TXN),
        .TXP                    (TXP),
        .TXRUNDISP              (),

        .CHBONDI                (4'b0),
        .CONFIGENABLE           (1'b0),
        .CONFIGIN               (1'b0),
        .ENCHANSYNC             (1'b0),
        .LOOPBACK               (LOOPBACK),
        .POWERDOWN              (POWERDOWN),
        .REFCLK                 (1'b0),
        .REFCLK2                (1'b0),
        .BREFCLK                (REFCLK),   //use BREFCLKs in implementation
        .BREFCLK2               (REFCLK2),
        .REFCLKSEL              (REFCLKSEL),
        .RXN                    (RXN),
        .RXP                    (RXP),
        .RXPOLARITY             (1'b0),
        .RXRESET                (RXRESET),
        .RXUSRCLK               (RXUSRCLK),
        .RXUSRCLK2              (RXUSRCLK2),
        .TXBYPASS8B10B          (TXBYPASS8B10B),
        .TXCHARDISPMODE         (TXCHARDISPMODE),
        .TXCHARDISPVAL          (TXCHARDISPVAL),
        .TXCHARISK              (TXCHARISK),
        .TXDATA                 (TXDATA),
        .TXFORCECRCERR          (1'b0),
        .TXINHIBIT              (TXINHIBIT),
        .TXPOLARITY             (1'b0),
        .TXRESET                (TXRESET),
        .TXUSRCLK               (TXUSRCLK),
        .TXUSRCLK2              (TXUSRCLK2)
      );


`endif

  //synthesis translate_off
  defparam MGT.TX_PREEMPHASIS                  = 1;
  defparam MGT.TX_DIFF_CTRL                    = 500;
  defparam MGT.TERMINATION_IMP                 = 50;
  defparam MGT.ALIGN_COMMA_MSB                 = "TRUE";
  defparam MGT.RX_DECODE_USE                   = "FALSE";
  defparam MGT.RX_BUFFER_USE                   = "TRUE";
  defparam MGT.TX_BUFFER_USE                   = "TRUE";
  defparam MGT.RX_DATA_WIDTH                   = 2;
  defparam MGT.TX_DATA_WIDTH                   = 2;
  defparam MGT.CLK_CORRECT_USE                 = "FALSE";
  defparam MGT.CHAN_BOND_MODE                  = "OFF";
  defparam MGT.TX_CRC_USE                      = "FALSE";
  defparam MGT.RX_CRC_USE                      = "FALSE";
  defparam MGT.PCOMMA_DETECT                   = "TRUE";
  defparam MGT.MCOMMA_DETECT                   = "FALSE";
  defparam MGT.DEC_PCOMMA_DETECT               = "FALSE";
  defparam MGT.DEC_MCOMMA_DETECT               = "FALSE";
  defparam MGT.DEC_VALID_COMMA_ONLY            = "FALSE";
  defparam MGT.SERDES_10B                      = "FALSE";
  defparam MGT.CLK_COR_KEEP_IDLE               = "FALSE";
  defparam MGT.CLK_COR_SEQ_LEN                 = 1;
  defparam MGT.CLK_COR_SEQ_2_USE               = "FALSE";
  defparam MGT.CLK_COR_INSERT_IDLE_FLAG        = "FALSE";
  defparam MGT.CLK_COR_REPEAT_WAIT             = 0;
  defparam MGT.CHAN_BOND_SEQ_LEN               = 1;
  defparam MGT.CHAN_BOND_SEQ_2_USE             = "FALSE";
  defparam MGT.CHAN_BOND_WAIT                  = 1;
  defparam MGT.CHAN_BOND_OFFSET                = 0;
  defparam MGT.CHAN_BOND_ONE_SHOT              = "FALSE";
  defparam MGT.CHAN_BOND_LIMIT                 = 1;
  defparam MGT.RX_LOSS_OF_SYNC_FSM             = "FALSE";
  defparam MGT.RX_LOS_INVALID_INCR             = 1;
  defparam MGT.RX_LOS_THRESHOLD                = 4;
  defparam MGT.CRC_FORMAT                      = "USER_MODE";
  defparam MGT.CRC_START_OF_PKT                = "K28_0";
  defparam MGT.CRC_END_OF_PKT                  = "K28_1";
  //synthesis translate_on

endmodule

`endif