led_pwm.v

这是用于xilinx virtex-2 pro产品的误码仪方案verilog HDL代码

///////////////////////////////////////////////////////////////////////////////
//
//    File Name:  LED_PWM.v
//      Version:  2.2
//         Date:  05/14/03
//        Model:  PWM Circuit to control LED intensity.
//                The LED_PWM is designed to produce different intensities on
//                an LED according to the value on intensity_in.  It connects
//                directly to a digital output, and works by using pulse width
//                modulation.
//
//      Company:  Xilinx, Inc.
//  Contributor:  Mike Matera
//
//   Disclaimer:  XILINX IS PROVIDING THIS DESIGN, CODE, OR
//                INFORMATION "AS IS" SOLELY FOR USE IN DEVELOPING
//                PROGRAMS AND SOLUTIONS FOR XILINX DEVICES.  BY
//                PROVIDING THIS DESIGN, CODE, OR INFORMATION AS
//                ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE,
//                APPLICATION OR STANDARD, XILINX IS MAKING NO
//                REPRESENTATION THAT THIS IMPLEMENTATION IS FREE
//                FROM ANY CLAIMS OF INFRINGEMENT, AND YOU ARE
//                RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY
//                REQUIRE FOR YOUR IMPLEMENTATION.  XILINX
//                EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH
//                RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION,
//                INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
//                REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE
//                FROM CLAIMS OF INFRINGEMENT, IMPLIED WARRANTIES
//                OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
//                PURPOSE.
//
//                (c) Copyright 2003 Xilinx, Inc.
//                All rights reserved.
//
///////////////////////////////////////////////////////////////////////////////

`ifdef LED_PWM `else 
`define LED_PWM

`timescale               100ps/10ps

module LED_PWM ( LED_out, intensity_in, reset_in, clock_in );
   //-------------------------------------------------------------
   // 
   // Port Summary:
   //
   // LED_out (synchronous: clock_in)
   //    Port to be connected to an IO driving an LED.
   //
   // intensity_in [03:00] (synchronous: clock_in)
   //    This is the four-bit intensity value input.
   //
   // reset_in (synchronous: clock_in)
   //    Synchronous reset.
   //
   // clock_in (clock: buffered)
   //    Clock.  
   // 
   //-------------------------------------------------------------
   input [3:0] intensity_in;
   output      LED_out;
   input       reset_in, clock_in;

   reg [7:0]   PWMBus;
   reg [3:0]   AddressCounter;
   reg         LED_out_prebuffer0, LED_out;

   wire [7:0]  RomWord;
   wire [3:0]  RomAddress;  
   wire        LED_out_prebuffer1;

   assign RomAddress[0] = AddressCounter[3];
   assign RomAddress[1] = intensity_in[3] ^ intensity_in[0];
   assign RomAddress[2] = intensity_in[3] ^ intensity_in[1];
   assign RomAddress[3] = intensity_in[3] ^ intensity_in[2];
   assign LED_out_prebuffer1 = intensity_in[3] ^ LED_out_prebuffer0;
   
   PWMRom pwm_memory ( .data_out(RomWord), .address_in(RomAddress) );

   always @ (AddressCounter[2:0] or PWMBus) begin
      case (AddressCounter[2:0]) 
        3'b000: LED_out_prebuffer0 <= PWMBus[0];
        3'b001: LED_out_prebuffer0 <= PWMBus[1];
        3'b010: LED_out_prebuffer0 <= PWMBus[2];
        3'b011: LED_out_prebuffer0 <= PWMBus[3];
        3'b100: LED_out_prebuffer0 <= PWMBus[4];
        3'b101: LED_out_prebuffer0 <= PWMBus[5];
        3'b110: LED_out_prebuffer0 <= PWMBus[6];
        3'b111: LED_out_prebuffer0 <= PWMBus[7];
      endcase
   end
      
   always @ (posedge clock_in) begin
      if (reset_in) begin 
         AddressCounter <= 0;
         LED_out <= 0;
         PWMBus <= 0;
      end else begin 
         AddressCounter <= AddressCounter + 1;
         LED_out <= LED_out_prebuffer1;
         PWMBus <= RomWord;
      end
   end   
endmodule

module PWMRom (data_out, address_in);
   output [7:0] data_out;
   input [3:0]  address_in;

   reg [7:0]    data_out; /* synthesis syn_romstyle = "select_rom" */
   
   // This implements the ROM:
   always @(address_in) begin
      case(address_in)
        4'b0000: data_out = 8'b00000000;
        4'b0001: data_out = 8'b00000000;

        4'b0010: data_out = 8'b10000000;
        4'b0011: data_out = 8'b00000000;

        4'b0100: data_out = 8'b10000000;
        4'b0101: data_out = 8'b10000000;

        4'b0110: data_out = 8'b10000100;
        4'b0111: data_out = 8'b00010000;

        4'b1000: data_out = 8'b10001000;
        4'b1001: data_out = 8'b10001000;

        4'b1010: data_out = 8'b10010010;
        4'b1011: data_out = 8'b01001000;

        4'b1100: data_out = 8'b10100100;
        4'b1101: data_out = 8'b10100100;

        4'b1110: data_out = 8'b10101010;
        4'b1111: data_out = 8'b10100100;

        default : data_out = 8'b00000000;
      endcase
   end
endmodule

`endif