phase_div.v

相位分频器源代码

/*******************************************************************************
** Module               : phase_div    

** Project              : SPWM Signal generator IP core

*******************************************************************************

** File                 : phase_div.v       

** Author               : liangyi        <[e-mail]>

**                        qinghuahuang   <[e-mail]>

**                        yaozhangchen   <[e-mail]>

** Creation Date        : 05/01/03                                              

** Last update          : 07/05/03

** Version Number       : 0.1                                                 

** Simulators           : Cadence_LDV

** Synthesizers         : LeonardoSpectrum

*******************************************************************************

** Description          : This module mainly distinguish the input addresses and
                          sign bits into three groups,and output them in different
                          time according to synchronization signals pipe1-pipe4.
                          Address is output ahead of sign bit by a cycle. 

*******************************************************************************/

module     phase_div(SYSCLK,reset_in,en,syn_addr_en,mark_red,mark_yellow,mark_blue,
                     addr_result_red,addr_result_yellow,addr_result_blue,
                     pipe2,pipe3,pipe4,pipe6,mark,address_in);

input         SYSCLK;                 //system clock
input         reset_in;               //global reset
input         en;                     //global enable
input         syn_addr_en;            //
input         mark_red;               //sign bit of red phase
input         mark_yellow;            //sign bit of yellow phase 
input         mark_blue;              //sign bit of blue phase
input  [8:0]  addr_result_red;        //the address of red phase
input  [8:0]  addr_result_yellow;     //the address of yellow phase
input  [8:0]  addr_result_blue;       //the address of blue phase

output        pipe2;                  //pipe1-pipe6 are synchronization signals  
output        pipe3;
output        pipe4;
output        pipe6;
output        mark;                   //the sign bit corresponds to the output address_in
output[8:0]   address_in;             //output address

reg   [8:0]   address_in;
reg           pipe1;
reg           pipe2;
reg           pipe3;
reg           pipe4;
reg           pipe5;
reg           pipe6;
reg           mark;

//shift register
always @(posedge SYSCLK )
   if(!reset_in)
      begin
         pipe1<=1'b0;
         pipe2<=1'b0;
         pipe3<=1'b0;
         pipe4<=1'b0;
         pipe5<=1'b0;
         pipe6<=1'b0;
      end

   else if(en)
      begin
         pipe1<=syn_addr_en;      //synchronization signal shift into shift-register
         pipe2<=pipe1;
         pipe3<=pipe2;
         pipe4<=pipe3;
         pipe5<=pipe4;
         pipe6<=pipe5;
       end
//output the address and sign bit of three phases
always@(posedge SYSCLK )
   if(!reset_in) 
      begin
        address_in<=9'd0;
        mark<=1'b0;
      end
   else 
      begin
        if(pipe1 && en)  
           begin                  
             address_in<=addr_result_red;   //output  the address of red phase
             mark<=mark_red;               //output the sign bit of red phase
           end
        else if (pipe2 && en)                       
           begin
             mark<=mark_yellow;               //output the sign bit of yellow phase
             address_in<=addr_result_yellow; //output  the address of yellow phase
           end

        else if (pipe3 && en)              
           begin
             mark<=mark_blue;            //output the sign bit of blue phase   
             address_in<=addr_result_blue; //output  the address of blue phase
           end
      end

endmodule