tb_pwm_ctl.v

学习verilog的一些资料。是脉宽调制控制的题目

`timescale 100ns/10ns
module tb_pwm_ctl;
reg rst,mclk,byte_sel,wr_n;
reg[7:0] db;
wire  pwm;
	test6 u1(.rst(rst),.mclk(mclk),.byte_sel(byte_sel),.wr_n(wr_n),.db(db),.pwm(pwm),.byte_rdy(byte_rdy));
	initial begin:init
		integer i;
		integer width;
		width=0;	i=0;
		rst=1;	mclk=0;
		byte_sel=1; wr_n=1;
		db=8'hzz;	
		#100 rst=0;
		#1500000 db=(20000/256); //150ms后写高字节
		#10 		wr_n=0;
		#110		wr_n=1;
		#10			db=8'hzz;
		#1500000 db=(20000%256); //再过150ms再写低字节，检查是否低字节写入之后控制量才起作用
					byte_sel=0;
		#10       wr_n=0;
		#110       wr_n=1;
		#10			db=8'hzz;
		#2000000 db=0;	byte_sel=1;	 //200 ms后
		#10			wr_n=0;
		#100		wr_n=1;
		#10			db=8'hzz;
		#10			db=0; byte_sel=0;		//写入0检查是否被忽略
		#10			wr_n=0;
		#100		wr_n=1;
		#10			db=8'hzz;
		#4000000 db=8'hff;	byte_sel=1;
		#10			wr_n=0;
		#100		wr_n=1;
		#10			db=8'hzz;
		
		#10			db=8'hff; byte_sel=0;
		#10			wr_n=0;
		#100		wr_n=1;
		#10			db=8'hzz;
		//一般情况检查		
		for(i=0;i<12;i=i+1)	begin
			width=5000*(i+1);
			#2500000 db=width/256;	byte_sel=1;
			#10			wr_n=0;
			#110			wr_n=1;
			#10			db=8'hzz;			
			#10			db=width%256;	byte_sel=0;
			#10			wr_n=0;	
			#110		wr_n=1;
			#10			db=8'hzz;			
			end
		#5000000 $stop;
	end 
	
	always #5 mclk=!mclk;
		
endmodule