test6.v

学习verilog的一些资料。是脉宽调制控制的题目

// -------------------------------
`timescale 100ns/10ns

module test6 (	rst,
				mclk,
				byte_sel,
				wr_n,
				db,
				byte_rdy,
				pwm	);
// ------------------------------

input			rst;
input			mclk;
input			byte_sel;
input			wr_n;
input	[7:0]	db;


// -------------------------------

output			pwm;
output			byte_rdy;
// -------------------------------

reg		[15:0]	db_reg;
reg		[15:0]	db_reg_out;
reg		[3:0]	db_stat;
reg				byte_rdy;
reg				wr_n_reg;

reg		[16:0]	b_clk_cnt;
reg				b_clk;

reg		[15:0]	pwm_cnt;
reg				pwm_reg;
reg				pwm;
reg		[1:0]	pwm_stat;

// -------------------------------

parameter	IDLE 		= 4'B0001;
parameter	GET_H_IS_0 	= 4'B0010;
parameter	GET_H_IS_1	= 4'B0100;
parameter	GET_L		= 4'B1000;

parameter	WAIT	= 2'B01;
parameter	END		= 2'B10;



// ---STATE MACHINE FOR DB --------

always @ (posedge mclk)
begin
	if(rst)
		begin
		db_stat	<= IDLE;
		db_reg		<= 16'h0000;
		byte_rdy	<= 1'b0;
		db_reg_out	<= 16'd50000;
		end
	else case(db_stat)
		IDLE:
			if( (!wr_n_reg)&&(byte_sel) )							// write high 8 bits
				begin
					if(db[7:0]==8'h00)
						begin
							db_stat			<= GET_H_IS_0 ;			// high is 0
							byte_rdy 		<= 1'b0 ;
						end
					else
						begin										// high is not 0
							db_reg[15:8]	<= db[7:0];
							db_stat			<= GET_H_IS_1 ;
							byte_rdy 		<= 1'b0 ;
						end
				end
		GET_H_IS_0:													// state for high byte is 0
			if( (!wr_n_reg)&&(!byte_sel) )
				begin
					if( db[7:0] == 8'h00 )
						begin
							db_stat		<= IDLE ;					// low byte is 0 , back to idle
							byte_rdy 	<= 1'b0 ;
						end
					else
						begin
							db_reg[15:0]<= {8'h00,db[7:0]};			// low byte is not 0, go to GET_L
							byte_rdy	<= 1'b0;
							db_stat		<= GET_L ;
						end
				end
		GET_H_IS_1:													// state for high byte is not 0
			if( (!wr_n_reg)&&(!byte_sel) )
				begin
					db_reg[7:0]<= db[7:0];
					byte_rdy	<= 1'b0;
					db_stat		<= GET_L ;
				end
		GET_L:
			begin
				db_stat		<= IDLE ;
				byte_rdy 	<= 1'b1 ;
				db_reg_out  <= db_reg;
			end
		endcase
end

// --- synchronize wr_n ---------

always @ (posedge mclk)
begin
	if(rst)
		wr_n_reg	<= 1'b1;
	else
		wr_n_reg	<= wr_n;
end

// --------generate bclk 1:99999-----

always @(posedge mclk)
begin
	if(rst)
		b_clk_cnt 	<= 0;
	else
		if(b_clk_cnt >= 17'd99999)
			b_clk_cnt <= 17'd0;
		else
			b_clk_cnt <= b_clk_cnt + 1'b1;
end

always @(posedge mclk)
begin
	if(rst)
		b_clk <= 1'b0;
	else
		if(b_clk_cnt == 17'd0)
			b_clk <= 1'b1;
		else
			b_clk <= 1'b0;
end

// ---------------------------------

always @(posedge mclk)
begin
	if(rst)
		begin
			pwm_stat<= WAIT;
			pwm_reg <= 1'b0;
			pwm_cnt <= 16'd0;			
		end
	else case ( pwm_stat )
		WAIT:
		if(!b_clk)
			begin
				if( pwm_cnt>=db_reg_out )
					begin
						pwm_reg <= 1'b0;
						pwm_stat<= END;
					end
				else
					begin
						pwm_reg <= 1'b1;
						pwm_cnt <= pwm_cnt + 1'b1;
					end
			end
		END:
		if( b_clk )
			begin
				pwm_cnt <= 16'd0;
				pwm_reg	<= 1'b0;
				pwm_stat<= WAIT;
			end
		endcase
end

always @ (posedge mclk)
pwm <= pwm_reg;

endmodule