halfband.v

verilog写的39阶通带为20KHz的半带fir滤波器

// halfband.v
module halfband(halfband_in,halfband_out,clk_96,reset);
	input[15:0] halfband_in;
	input clk_96;
    input reset;
	output[15:0] halfband_out;
	wire [15:0] halfband_out;
	reg[15:0] tap1,tap2,tap3,tap4,tap5,tap6,tap7,tap8,tap9,tap10,tap11,tap12,tap13,tap14,tap15,tap16,tap17,tap18,tap19,tap20,tap21,tap22,tap23,tap24,tap25,tap26,tap27,tap28,tap29,tap30,tap31,tap32,tap33,tap34,tap35,tap36,tap37,tap38,tap39;

	wire[30:0] t1,t3,t5,t7,t9,t11,t13,t15,t17,t19,t20,t21,t23,t25,t27,t29,t31,t33,t35,t37,t39;
	wire[31:0] sum1,sum2,sum3,sum4,sum5,sum6,sum7,sum8,sum9,sum10,sum11,sum12,sum13,sum14,sum15,sum16,sum17,sum18,sum19,sum20;
    wire[31:0] convert;
    reg[31:0] out_r;
    parameter  coeff1=16'b1111111111010010,
        coeff2=16'b0000000000000000, 
        coeff3=16'b0000000001010111, 
        coeff4=16'b0000000000000000, 
        coeff5=16'b1111111101011011, 
        coeff6=16'b0000000000000000, 
        coeff7=16'b0000000100011101, 
        coeff8=16'b0000000000000000, 
        coeff9=16'b1111111000110010, 
        coeff10=16'b0000000000000000,
        coeff11=16'b0000001011010100,
        coeff12=16'b0000000000000000,
        coeff13=16'b1111101110011001,
        coeff14=16'b0000000000000000,
        coeff15=16'b0000011100010100,
        coeff16=16'b0000000000000000,
        coeff17=16'b1111001100010110, 
        coeff18=16'b0000000000000000,
        coeff19=16'b0010100010000101,
        coeff20=16'b0100000000000000, 
        coeff21=16'b0010100010000101, 
        coeff22=16'b0000000000000000, 
        coeff23=16'b1111001100010110, 
        coeff24=16'b0000000000000000,
        coeff25=16'b0000011100010100, 
        coeff26=16'b0000000000000000, 
        coeff27=16'b1111101110011001,
        coeff28=16'b0000000000000000,
        coeff29=16'b0000001011010100, 
        coeff30=16'b0000000000000000,
        coeff31=16'b1111111000110010, 
        coeff32=16'b0000000000000000, 
        coeff33=16'b0000000100011101, 
        coeff34=16'b0000000000000000,
        coeff35=16'b1111111101011011, 
        coeff36=16'b0000000000000000,
        coeff37=16'b0000000001010111,
        coeff38=16'b0000000000000000,
        coeff39=16'b1111111111010010;

	always@ (posedge clk_96 or posedge reset)
		begin
            if(reset)
            begin
    		    tap1<=16'b0;
                tap2<=16'b0;
                tap3<=16'b0;
                tap4<=16'b0;
                tap5<=16'b0;
                tap6<=16'b0;
                tap7<=16'b0;
                tap8<=16'b0;
                tap9<=16'b0;
                tap10<=16'b0;
                tap11<=16'b0;
                tap12<=16'b0;
                tap13<=16'b0;
                tap14<=16'b0;
                tap15<=16'b0;
                tap16<=16'b0;
                tap17<=16'b0;
                tap18<=16'b0;
                tap19<=16'b0;
                tap20<=16'b0;
                tap21<=16'b0;
                tap22<=16'b0;
                tap23<=16'b0;
                tap24<=16'b0;
                tap25<=16'b0;
                tap26<=16'b0;
                tap27<=16'b0;
                tap28<=16'b0;
                tap29<=16'b0;
                tap30<=16'b0;
                tap31<=16'b0;
                tap32<=16'b0;
                tap33<=16'b0;
                tap34<=16'b0;
                tap35<=16'b0;
                tap36<=16'b0;
                tap37<=16'b0;
                tap38<=16'b0;
                tap39<=16'b0;
           end
		 else
            begin
                tap1<=halfband_in;
                tap2<=tap1;
                tap3<=tap2;
                tap4<=tap3;
                tap5<=tap4;
                tap6<=tap5;
                tap7<=tap6;
                tap8<=tap7;
                tap9<=tap8;
                tap10<=tap9;
                tap11<=tap10;
                tap12<=tap11;
                tap13<=tap12;
                tap14<=tap13;
                tap15<=tap14;
                tap16<=tap15;
                tap17<=tap16;
                tap18<=tap17;
                tap19<=tap18;
                tap20<=tap19;
                tap21<=tap20;
                tap22<=tap21;
                tap23<=tap22;
                tap24<=tap23;
                tap25<=tap24;
                tap26<=tap25;
                tap27<=tap26;
                tap28<=tap27;
                tap29<=tap28;
                tap30<=tap29;
                tap31<=tap30;
                tap32<=tap31;
                tap33<=tap32;
                tap34<=tap33;
                tap35<=tap34;
                tap36<=tap35;
                tap37<=tap36;
                tap38<=tap37;
                tap39<=tap38;
            end
        end
    assign t1=tap1*coeff1;
    assign t3=tap3*coeff3;
    assign t5=tap5*coeff5;
    assign t7=tap7*coeff7;
    assign t9=tap9*coeff9;
    assign t11=tap11*coeff11;
    assign t13=tap13*coeff13;
    assign t15=tap15*coeff15;
    assign t17=tap17*coeff17;
    assign t19=tap19*coeff19;
    assign t20=tap20*coeff20;
    assign t21=tap21*coeff21;
    assign t23=tap23*coeff23;
    assign t25=tap25*coeff25;
    assign t27=tap27*coeff27;
    assign t29=tap29*coeff29;
    assign t31=tap31*coeff31;
    assign t33=tap33*coeff33;
    assign t35=tap35*coeff35;
    assign t37=tap37*coeff37;
    assign t39=tap39*coeff39;
    assign sum1=t1+t3;
    assign sum2=sum1+t5;
    assign sum3=sum2+t7;
    assign sum4=sum3+t9;
    assign sum5=sum4+t11;
    assign sum6=sum5+t13;
    assign sum7=sum6+t15;
    assign sum8=sum7+t17;
    assign sum9=sum8+t19;
    assign sum10=sum9+t20;
    assign sum11=sum10+t21;
    assign sum12=sum11+t23;
    assign sum13=sum12+t25;
    assign sum14=sum13+t27;
    assign sum15=sum14+t29;
    assign sum16=sum15+t31;
    assign sum17=sum16+t33;
    assign sum18=sum17+t35;
    assign sum19=sum18+t37;
    assign sum20=sum19+t39;
    assign convert=sum20;
    always@(posedge clk_96 or posedge reset)
        begin
            if(reset)
                out_r<=32'b0;
            else 
                out_r<=convert;
        end
    assign halfband_out=out_r[31:16];
endmodule