_primary.vhd

it is a verilog code written for traffic light controller will synthesize in xinlix ise 8.2i.i have

library verilog;
use verilog.vl_types.all;
entity cnter_enb_ovf is
    generic(
        bits            : integer := 26;
        max             : integer := 40000000
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        enable          : in     vl_logic;
        overflow        : out    vl_logic;
        cnt_val         : out    vl_logic_vector
    );
end cnter_enb_ovf;