_primary.vhd

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

library verilog;
use verilog.vl_types.all;
entity ram_blk is
    generic(
        ram_width       : integer := 8;
        ram_addr_bits   : integer := 5
    );
    port(
        clk             : in     vl_logic;
        wrt_sig         : in     vl_logic;
        addr_w          : in     vl_logic_vector;
        addr_r          : in     vl_logic_vector;
        din_ram         : in     vl_logic_vector;
        dout_ram        : out    vl_logic_vector
    );
end ram_blk;