_primary.vhd

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

library verilog;
use verilog.vl_types.all;
entity fifo_top is
    generic(
        depth           : integer := 32
    );
    port(
        clk             : in     vl_logic;
        rst_n           : in     vl_logic;
        wrt_sig         : in     vl_logic;
        rd_sig          : in     vl_logic;
        din             : in     vl_logic_vector(7 downto 0);
        full_sig        : out    vl_logic;
        empty_sig       : out    vl_logic;
        over_flow       : out    vl_logic;
        under_flow      : out    vl_logic;
        dout            : out    vl_logic_vector(7 downto 0)
    );
end fifo_top;