_primary.vhd

it is a verilog code written for FIFO in modelsim simulator and it will synthesize in xinlix ise 8

library verilog;
use verilog.vl_types.all;
entity ram_32x8 is
    generic(
        depth           : integer := 32;
        width           : integer := 8
    );
    port(
        clk             : in     vl_logic;
        wrt_sig         : in     vl_logic;
        addr_w          : in     vl_logic_vector(4 downto 0);
        addr_r          : in     vl_logic_vector(4 downto 0);
        din_ram         : in     vl_logic_vector(7 downto 0);
        dout_ram        : out    vl_logic_vector(7 downto 0)
    );
end ram_32x8;