_primary.vhd

来自「it is a verilog code written for FIFO i」· VHDL 代码 · 共 9 行

library verilog;
use verilog.vl_types.all;
entity fifo_tb is
    generic(
        total_bytes     : integer := 31;
        ram_type        : integer := 0
    );
end fifo_tb;