adc_top.v

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : adc_top.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

module adc_top(// Inputs
               clk,
               rst_n,
               ai_sel_sig,
               adc_strobe_p,
               adc_data_o,
               // Outputs
               adc_sclk,     // Serial Clock input to ADC
               adc_cs,       // ADC Chip select
               adc_din,      // Tx Channel Number for sampling...
               data_out
              );
//====== Port Declaration ========//
input         clk ;
input         rst_n ;
input [3:0]   ai_sel_sig ;
input         adc_strobe_p ;
input         adc_data_o ;

output        adc_sclk ;
output        adc_cs ;
output        adc_din ;
output [14:0] data_out ;


wire        clk_2MHz ;
wire [15:0] data_frm_ai ;
wire        data_frm_ai_rdy ;
wire [7:0]  adc_val_volts ;


// Clock Divider Core
adc_clk_div adc_clk_div_inst(// Inputs
                             .clk            (clk     ),
                             .rst_n          (rst_n   ),
                             // Output
                             .clk_2MHz       (clk_2MHz)
                            );

// Analog Inputs Controller (ADC Interface)
adc_interface adc_interface_inst(// Inputs
                                 .clk_2MHz              (clk_2MHz       ),
                                 .rst_n                 (rst_n          ),
                                 .ai_sel_sig            (ai_sel_sig     ),   // 4-bit Signal Requst from main State Machine ({ch_num[3:1],enb[0]}) (3-bit channel number & 1-bit enable)
                                 .adc_strobe_p          (adc_strobe_p   ),   // Serial Strobe Output from ADC to check ADC is in conversion state or not
                                 .adc_data_o            (adc_data_o     ),   // Sampled Data out from ADC
                                 // Outputs
                                 .adc_sclk              (adc_sclk       ),   // Serial Clock input to ADC
                                 .adc_cs                (adc_cs         ),   // ADC Chip select
                                 .adc_din               (adc_din        ),   // Tx Channel Number for sampling...
                                 .data_frm_ai           (data_frm_ai    ),
                                 .data_frm_ai_rdy       (data_frm_ai_rdy)
                                );

// Lookup Table for ADC Data
adc_lut adc_lut_inst(// Inputs
                     .clk                  (clk              ),
                     .rst_n                (rst_n            ),
                     .montring_enb         (ai_sel_sig[0]    ),
                     .adc_data_rdy         (data_frm_ai_rdy  ),
                     .adc_data             (data_frm_ai[11:0]),
                     // Outputs
                     .adc_val_volts        (adc_val_volts    )
                    );

// BCD to Seven Segment Decoder
adc_bcd27seg_dec adc_bcd27seg_dec_inst(// Input
                                       .clk                  (clk          ),
                                       .rst_n                (rst_n        ),
                                       .data_in              (adc_val_volts),
                                       .data_rdy             (ai_sel_sig[0]),
                                       // Output
                                       .data_out             (data_out     )
                                      );

endmodule