adc_interface.v

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : adc_interface.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

// Analog Inputs Controller (ADC Interface)
module adc_interface(// Inputs
                     clk_2MHz,
                     rst_n,
                     ai_sel_sig,   // 4-bit Signal Requst from main State Machine ({ch_num[3:1],enb[0]}) (3-bit channel number & 1-bit enable)
                     adc_strobe_p, // Serial Strobe Output from ADC to check ADC is in conversion state or not
                     adc_data_o,   // Sampled Data out from ADC
                     // Outputs
                     adc_sclk,     // Serial Clock input to ADC
                     adc_cs,       // ADC Chip select
                     adc_din,      // Tx Channel Number for sampling...
                     data_frm_ai,
                     data_frm_ai_rdy
                    );
//====== Port Declaration ========//
input         clk_2MHz ;
input         rst_n ;
input [3:0]   ai_sel_sig ;
input         adc_strobe_p ;
input         adc_data_o ;

output        adc_sclk ;
output        adc_cs ;
output        adc_din ;
output [15:0] data_frm_ai ;
output        data_frm_ai_rdy ;

reg [1:0]  clk_cnt ;
reg [2:0]  sel_ch ;
reg        adc_sclk ;
reg        adc_sclk_r ;
reg        adc_cs ;
reg        adc_cs_r1 ;
reg        adc_cs_r2 ;
reg        adc_cs_r3 ;
reg [7:0]  shift_reg_tx ;
reg        adc_din ;
reg [14:0] shift_reg_rx ;
reg [3:0]  cnt_bits ;
reg [15:0] data_frm_ai ;
reg        data_frm_ai_sig ;
reg        data_frm_ai_rdy ;
reg [2:0]  wach_dog_cnt ;

wire       clk_1MHz ;
wire       adc_cs_sig ;
wire       sel_ch_sig ;
wire       ld_data_sig ;
wire       tx_data_sig ;
wire       wait_strobe_sig ;
wire       rx_data_sig ;
wire       rxdata_valid_sig ;
wire       adc_scan_comp_sig ;


always @(posedge clk_2MHz or negedge rst_n)
begin
   if(~rst_n)
      clk_cnt <= #1 2'b0 ;
   else
      clk_cnt <= #1 clk_cnt + 1 ;
end

assign clk_1MHz = clk_cnt[0] ;

// Counter that counts Tx bits to ADC and Rx bits from ADC
always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      cnt_bits <= #1 4'd0 ;
   else if(tx_data_sig | rx_data_sig)
      cnt_bits <= #1 cnt_bits + 1 ;
   else
      cnt_bits <= #1 4'd0 ;
end   

always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      sel_ch <= #1 3'd0 ;
   else if(sel_ch_sig)
      sel_ch <= #1 ai_sel_sig[3:1] ;
   else
      sel_ch <= #1 3'd0 ;
end   

//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++++++++ Data Tx to ADC ++++++++++++++++++++++++++
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk_2MHz or negedge rst_n)
begin
   if(~rst_n) begin
      adc_sclk <= #1 1'b0 ;
      adc_cs_r1 <= #1 1'b1 ;
      adc_cs_r2 <= #1 1'b1 ;
      adc_cs_r3 <= #1 1'b1 ;
      adc_cs <= #1 1'b1 ;
   end
   else begin
      adc_sclk <= #1 adc_sclk_r ;
      adc_cs_r1 <= #1 adc_cs_sig ;
      adc_cs_r2 <= #1 adc_cs_r1 ;
      adc_cs_r3 <= #1 adc_cs_r2 ;
      adc_cs <= #1 adc_cs_r3 ;
   end
end

always @(posedge clk_2MHz or negedge rst_n)
begin
   if(~rst_n)
      adc_sclk_r <= #1 1'b0 ;
   else if(~(adc_cs | adc_cs_sig))
      adc_sclk_r <= #1 clk_1MHz ;
   else
      adc_sclk_r <= #1 1'b0 ;
end

always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      shift_reg_tx <= #1 8'd0 ;
   else if(ld_data_sig)
      shift_reg_tx <= #1 {1'b1,sel_ch,4'b1111} ; // Start,Ch2,Ch1,Ch0,UNI/BIP,SGL/DIF,PD1,PD0
   else if(tx_data_sig)
      shift_reg_tx <= #1 {shift_reg_tx[6:0],1'b0} ;
   else
      shift_reg_tx <= #1 shift_reg_tx ;
end

always @(posedge clk_2MHz or negedge rst_n)
begin
   if(~rst_n)
      adc_din <= #1 1'b0 ;
   else
      adc_din <= #1 shift_reg_tx[7] ;
end   
//++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
//+++++++++++++++++++++ Data Rx to ADC ++++++++++++++++++++++++++
//+++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      shift_reg_rx <= #1 15'd0 ;
   else if(rx_data_sig)
      shift_reg_rx <= #1 {shift_reg_rx[13:0],adc_data_o} ;
   else
      shift_reg_rx <= #1 shift_reg_rx ;
end

// Received Data sent to Input Memory
always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n) begin
      data_frm_ai <= #1 16'd0 ;
      data_frm_ai_sig <= #1 1'b0 ;
   end
   else if(rxdata_valid_sig) begin
      data_frm_ai <= #1 {1'b0,sel_ch,shift_reg_rx[14:3]} ;
      data_frm_ai_sig <= #1 1'b1 ;
   end
   else begin
      data_frm_ai <= #1 data_frm_ai ;
      data_frm_ai_sig <= #1 1'b0 ;
   end
end

always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      data_frm_ai_rdy <= #1 1'b0 ;
   else
      data_frm_ai_rdy <= #1 data_frm_ai_sig ;
end

always @(posedge clk_1MHz or negedge rst_n)
begin
   if(~rst_n)
      wach_dog_cnt <= #1 3'd0 ;
   else if(wait_strobe_sig)
      wach_dog_cnt <= #1 wach_dog_cnt + 1 ;
   else
      wach_dog_cnt <= #1 3'd0 ;  
end


// ADC Controller (State Machine)
adc_max186_sm adc_max186_sm_inst(// Inputs
                                 .clk_1MHz                  (clk_1MHz         ),
                                 .rst_n                     (rst_n            ),
                                 .ai_enb_sig                (ai_sel_sig[0]    ), 
                                 .adc_strobe_p              (adc_strobe_p     ),
                                 .cnt_bits                  (cnt_bits         ),
                                 .wach_dog_cnt              (wach_dog_cnt     ),
                                 // Outputs
                                 .sel_ch_sig                (sel_ch_sig       ),
                                 .adc_cs_sig                (adc_cs_sig       ),
                                 .ld_data_sig               (ld_data_sig      ),
                                 .tx_data_sig               (tx_data_sig      ),
                                 .wait_strobe_sig           (wait_strobe_sig  ),
                                 .rx_data_sig               (rx_data_sig      ),
                                 .rxdata_valid_sig          (rxdata_valid_sig ),
                                 .adc_scan_comp_sig         (adc_scan_comp_sig)
                                );
endmodule