adc_clk_div.v

it is a verilog code written for MAX1886 ADC interin modelsim simulator and it will synthesize in x

//*****************************************************************************************//
//    Project      : FPGA based Digital Design using Verilog HDL
//    File         : adc_top.v
//    Author       : Irfan Faisal Mir & Nauman Mir
//    Company      : Chip Designing Course
//    Start Date   : 
//    Last Updated : 
//    Version      : 0.1
//    Abstract     : This module implements...........
// 
//    Modification History:
//==========================================================================================
//    Date                       By                    Version            Change Description
//==========================================================================================
//                               Irfan & Nauman        0.1                Original Version
//
//******************************************************************************************//

// Clock Divider Core
module adc_clk_div(// Inputs
                   clk,
                   rst_n,
                   // Output
                   clk_2MHz
                  );
//====== Port Declaration ========//
input         clk ;
input         rst_n ;

output        clk_2MHz ;

reg [1:0] count_div ;
reg       clk_2MHz ;

always @(posedge clk or negedge rst_n)
begin
   if(~rst_n) begin
      count_div <= #1 2'd0 ;
      clk_2MHz <= #1 1'b0 ;
   end
   else if(count_div == 2'd3) begin
      count_div <= #1 2'd0 ;
      clk_2MHz <= #1 ~clk_2MHz ;
   end  
   else begin
      count_div <= #1 count_div + 1 ;
      clk_2MHz <= #1 clk_2MHz ;
   end
end

endmodule