obufds_lde_lvds.edf

xilinx LVDS接口程序,xilinx LVDS接口程序

(edif Xilinx_edif (edifVersion 2 0 0) (edifLevel 0)
 (keywordMap (keywordLevel 0))
 (status
  (written (timeStamp 2000 2 23 16 35 10)
   (program "Xilinx" (Version "2.23.2000"))
   (dataOrigin "Xilinx") (author "XAPP133")
  )
 )
 (external (rename xfpga_virtexe_7 "xfpga_virtexe-7") (edifLevel 0)
  (technology (numberDefinition))
  (cell INV (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
  (cell OBUF_LVDS (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port O (direction OUTPUT)) (port I (direction INPUT)))
   )
  )
  (cell LDCE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port G (direction INPUT)) (port GE (direction INPUT))
     (port CLR (direction INPUT))
    )
   )
  )
  (cell LDPE (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port Q (direction OUTPUT)) (port D (direction INPUT))
     (port G (direction INPUT)) (port GE (direction INPUT))
     (port PRE (direction INPUT))
    )
   )
  )
 )
 (library DESIGNS (edifLevel 0) (technology (numberDefinition))
  (cell GND (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port G (direction OUTPUT)))
   )
  )
  (cell OBUFDS_LDE_LVDS (cellType GENERIC)
   (view Netlist_representation (viewType NETLIST)
    (interface (port D (direction INPUT)) (port GE (direction INPUT))
     (port G (direction INPUT)) (port O (direction OUTPUT))
     (port OB (direction OUTPUT))
    )
    (contents (instance Logic0 (viewRef Netlist_representation (cellRef GND)))
     (instance inv_n
      (viewRef Netlist_representation
       (cellRef INV (libraryRef xfpga_virtexe_7))
      )
     )
     (instance pad_p
      (viewRef Netlist_representation
       (cellRef OBUF_LVDS (libraryRef xfpga_virtexe_7))
      )
     )
     (instance pad_n
      (viewRef Netlist_representation
       (cellRef OBUF_LVDS (libraryRef xfpga_virtexe_7))
      )
     )
     (instance olatch_p
      (viewRef Netlist_representation
       (cellRef LDCE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (instance olatch_n
      (viewRef Netlist_representation
       (cellRef LDPE (libraryRef xfpga_virtexe_7))
      )
      (property IOB (string "true"))
     )
     (net CLR
      (joined (portRef CLR (instanceRef olatch_p))
       (portRef PRE (instanceRef olatch_n)) (portRef G (instanceRef Logic0))
      )
     )
     (net D
      (joined (portRef D) (portRef I (instanceRef inv_n))
       (portRef D (instanceRef olatch_p))
      )
     )
     (net q_n
      (joined (portRef Q (instanceRef olatch_n))
       (portRef I (instanceRef pad_n))
      )
     )
     (net GE
      (joined (portRef GE) (portRef GE (instanceRef olatch_p))
       (portRef GE (instanceRef olatch_n))
      )
     )
     (net q_p
      (joined (portRef Q (instanceRef olatch_p))
       (portRef I (instanceRef pad_p))
      )
     )
     (net G
      (joined (portRef G) (portRef G (instanceRef olatch_p))
       (portRef G (instanceRef olatch_n))
      )
     )
     (net OB (joined (portRef OB) (portRef O (instanceRef pad_n))))
     (net D_n
      (joined (portRef O (instanceRef inv_n))
       (portRef D (instanceRef olatch_n))
      )
     )
     (net O (joined (portRef O) (portRef O (instanceRef pad_p))))
    )
   )
  )
 )
 (design Xilinx_edif (cellRef OBUFDS_LDE_LVDS (libraryRef DESIGNS)))
)