top.vhd

实现嵌入式系统的秒表计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;

entity top is
     port( clk_1M: in std_logic;       --1M晶振输入
           fun_key: in std_logic;       
           set_key: in std_logic;   
          bell_key: in std_logic;
           over_key:in std_logic;
            sel_1: out std_logic_vector(5 downto 0);  
            seg_show: out std_logic_vector(6 downto 0);
            sound_out:out std_logic;
             am_pm: out std_logic);
end;
architecture behav of top is        
 signal    clk_1HZ : std_logic;         --用于连接各模块的信号
 signal  clk_1K : std_logic;
 signal   sk_out : std_logic;
 signal     bk_out : std_logic;
  signal     over_out:std_logic;
 signal      bs : std_logic;
 signal   bell_out : std_logic;
 signal  cur_state : integer range 0 to 4;
 signal        csl : integer range 0 to 9;
 signal        csh : integer range 0 to 5; 
 signal        chl : integer range 0 to 9;
 signal        chh : integer range 0 to 2;
 signal        cml : integer range 0 to 9;
 signal        cmh : integer range 0 to 5;
 signal        ch1 : integer range 0 to 9;
 signal        ch2 : integer range 0 to 2;
 signal     bell_h1: integer range 0 to 9;--设置闹钟时的时间参数
 signal     bell_h2: integer range 0 to 2;
 signal     bell_m1: integer range 0 to 9;
 signal     bell_m2: integer range 0 to 5;
 signal     bell_s1: integer range 0 to 9;
 signal     bell_s2: integer range 0 to 5;
 signal     bell_en: std_logic; 

component input is                       
      port( clk_1M : in  std_logic;      
                fk : in  std_logic; 
            clk_1K : out std_logic;
           clk_1HZ : out std_logic;
             state : out integer range 0 to 4);
end component;

component all_count is                       
    port(     set : in std_logic;
              ter :in std_logic;
             state : in integer range 0 to 4;
            clk_1HZ : in std_logic;
                 s_low: out integer range 0 to 9;
                 s_high : out integer range 0 to 5;
                 m_low : out integer range 0 to 9;
                 m_high : out integer range 0 to 5;
                 h_low : out integer range 0 to 9;
                 h_high : out integer range 0 to 2;
                bs : out std_logic;
              bell_out : out std_logic;
            bell_h1: in integer range 0 to 9;
             bell_h2: in integer range 0 to 2;
             bell_m1: in integer range 0 to 9;
             bell_m2: in integer range 0 to 5;
             bell_s1: in integer range 0 to 9;
             bell_s2: in integer range 0 to 5
          );
end component;

component display is                       
    port(    clk_1K : in std_logic;  
            csl : in integer range 0 to 9; 
            csh : in integer range 0 to 5;
            cml : in integer range 0 to 9;
            cmh : in integer range 0 to 5; 
            chl : in integer range 0 to 9;  
            chh : in integer range 0 to 2; 
         bell_h1: in integer range 0 to 9;
         bell_h2: in integer range 0 to 2;
         bell_m1: in integer range 0 to 9;
         bell_m2: in integer range 0 to 5;
         bell_s1: in integer range 0 to 9;
         bell_s2: in integer range 0 to 5;
         bell_en: in  std_logic; 
            sel_1 : out std_logic_vector(5 downto 0);  
            seg_show : out std_logic_vector(6 downto 0));
end component;

component bell is                        --bell为闹钟模块
port(
      bell_key:in std_logic;
       set_key:in std_logic;
       bell_h1:out integer range 0 to 9;
       bell_h2:out integer range 0 to 2;
       bell_m1:out integer range 0 to 9;
       bell_m2:out integer range 0 to 5;
       bell_s1:out integer range 0 to 9;
       bell_s2:out integer range 0 to 5;
       bell_en:out std_logic);
end component;


   

begin
sk_out<=set_key;
bk_out<=bell_key;
over_out<=over_key;
u1:input port map(clk_1M,fun_key,clk_1K,clk_1HZ,cur_state);

u2:all_count port map(sk_out,over_out,cur_state,clk_1HZ,csl,csh,cml,cmh,chl,chh,bs,bell_out,bell_h1,bell_h2,bell_m1,bell_m2,bell_s1,bell_s2);

u3:process(cur_state,chh,chl)                --12/24小时切换的实现
begin
if ( cur_state=4 ) then 
 if( chh>0 and chl>1 ) then
 ch2<=chh-1;ch1<=chl-2;
 am_pm<='0';--下午
 elsif(chh=2 and chl=1) then
 ch2<=0;ch1<=9;
 am_pm<='0';--下午
 elsif( chh=2 and chl=0) then
 ch2<=0;ch1<=8;
 am_pm<='0';--afternoon
 else ch2<=chh;ch1<=chl;
 am_pm<='1';--morning
 end if;
else 
ch2<=chh;ch1<=chl;
if(chh>0 and chl>2) then
am_pm<='0';
else am_pm<='1';
end if;
end if;
 end process;

u4:display port map(clk_1K,csl,csh,cml,cmh,ch1,ch2,bell_h1,bell_h2,bell_m1,bell_m2,bell_s1,bell_s2,bell_en,sel_1,seg_show);

u5:bell port map(bk_out,sk_out,bell_h1,bell_h2,bell_m1,bell_m2,bell_s1,bell_s2,bell_en);

u6:process(bell_out,bs)                       
   begin
   if(bell_out='1') then
       sound_out<='1';
   elsif(bs='1') then
       sound_out<='1';
   else
       sound_out<='0';
   end if;
end process;
end;