input.vhd

实现嵌入式系统的秒表计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity input is
port(
clk_1M:in std_logic;
fk : in std_logic;  
clk_1K:out std_logic;
clk_1HZ:out std_logic;
state  : out integer range  0 to 4
);
end input;

architecture input_arch of input is
signal clk_100K:std_logic;
signal clk_10K:std_logic;
signal clk_1K_temp:std_logic;
signal clk_100HZ:std_logic;
signal clk_1HZ_temp:std_logic;
signal st:integer range 0 to 4;
signal key:std_logic;

begin
key<=fk;
p1:process(clk_1M)
variable count1:integer range 0 to 4;
   begin
if (clk_1M'event and clk_1M='1')then
   if(count1=4)then
     clk_100K<=not clk_100K;
     count1:=0;
    else 
       count1:=count1+1;
    end if;
end if;
end process;

p2:process(clk_100K)
variable count2:integer range 0 to 4;
   begin
if (clk_100K'event and clk_100K='1')then
   if(count2=4)then
     clk_10K<=not clk_10K;
     count2:=0;
    else 
       count2:=count2+1;
    end if;
end if;
end process;

p3:process(clk_10K)
variable count3:integer range 0 to 4;
   begin
if (clk_10K'event and clk_10K='1')then
   if(count3=4)then
     clk_1K_temp<=not clk_1K_temp;
     count3:=0;
    else 
       count3:=count3+1;
    end if;
end if;
clk_1K<=clk_1K_temp;
end process;

p4:process(clk_1K_temp)
variable count4:integer range 0 to 4;
   begin
if (clk_1K_temp'event and clk_1K_temp='1')then
   if(count4=4)then
     clk_100HZ<=not clk_100HZ;
     count4:=0;
    else 
       count4:=count4+1;
    end if;
end if;
end process;

 p5:process(clk_100HZ)
variable count5:integer range 0 to 49;
   begin
if (clk_100HZ'event and clk_100HZ='1')then
   if(count5=49)then
     clk_1HZ_temp<=not clk_1HZ_temp;
     count5:=0;
    else 
       count5:=count5+1;
    end if;
end if;
  clk_1HZ<=clk_1HZ_temp;
end process;

p6:process(key,st) 
 begin
 if(key'event and key='1') then   
     if(st=4) then st<=0;            
     else st<=st+1;                 
     end if;                        
 end if;                           
state<=st;                           
end process;                      
end;