hour.vhd

实现嵌入式系统的秒表计时

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_signed.all;
entity hour is
port
(clk_1HZ : in std_logic; 
 enable:in std_logic;
 h_low:out integer range 0 to 9;
 h_high:out integer range 0 to 2);
end;

architecture hour_arch of hour is
signal hl:integer range 0 to 9;
signal hh:integer range 0 to 2;
begin
process(clk_1HZ,enable)
begin
if(enable='0')then
null;
else
if(clk_1HZ'event and clk_1HZ='1')then
if(hl=3 and hh=2)then
hl<=0;
hh<=0;
elsif(hl/=9 and hh/=2)then
hl<=hl+1;
elsif(hl=9 and hh/=2)then
hl<=0;
hh<=hh+1;
elsif(hl/=3 and hh=2)then
hl<=hl+1;
else
hl<=0;hh<=0;
end if;
 end if;
end if;
end process;
h_low<=hl;h_high<=hh;
end;