bell.vhd

实现嵌入式系统的秒表计时

library ieee;                        --闹钟设置时复用了正常显示时的
use ieee.std_logic_1164.all;         --调时调分调秒模块
use ieee.std_logic_unsigned.all;
entity bell is
port(
      bell_key:in std_logic;
      set_key:in std_logic;
      bell_h1:out integer range 0 to 9;
      bell_h2:out integer range 0 to 2;
      bell_m1:out integer range 0 to 9;
      bell_m2:out integer range 0 to 5;
      bell_s1:out integer range 0 to 9;
      bell_s2:out integer range 0 to 5;
      bell_en:out std_logic);
end;

architecture behav of bell is
signal   c1: std_logic;
signal   c2: std_logic;
signal enh : std_logic; ----计时器计时允许信号
signal enm : std_logic;
signal ens : std_logic;
signal  cp : std_logic;  ----计时器工作时钟信号
signal  sl : integer range 0 to 9;
signal  sh : integer range 0 to 5;
signal  ml : integer range 0 to 9; 
signal  mh : integer range 0 to 5;
signal  hl : integer range 0 to 9;
signal  hh : integer range 0 to 2;
signal  bell_state:integer range 0 to 4;
signal  bell_enable:std_logic;

component second is  
port( clk_1HZ : in std_logic;
       enable : in std_logic;
      s_low:out integer range 0 to 9;
      s_high:out integer range 0 to 5;
      count:out std_logic); 
end component;


component minute is  
port( clk_1Hz : in std_logic;
       enable:in std_logic;
       m_low:out integer range 0 to 9;
      m_high:out integer range 0 to 5;
    count : out std_logic);
end component;

component hour is 
port( clk_1Hz : in std_logic;
       enable : in std_logic;
       h_low:out integer range 0 to 9;
        h_high:out integer range 0 to 2);
end component;

begin

p0:process(bell_key,bell_state)
begin
 if(bell_key'event and bell_key='1') then
  if(bell_state=4) then bell_state<=0;
     else bell_state<=bell_state + 1;
  end if;
 end if;
 if( bell_state=1 or bell_state=2 or bell_state=3) then 
    bell_enable<='1';
 else                  --bell_state为4时bell_enable置低，为闹钟设置完毕信号
    bell_enable<='0';
 end if;    
 end process ;
bell_en<=bell_enable;


p1:process(set_key,bell_state)
begin
if(bell_state=1)     then cp<=set_key;enh<='0';enm<='0' ; ens<='1';
elsif(bell_state=2)  then cp<=set_key;enh<='0';enm<='1';ens<='0';
elsif(bell_state=3)  then cp<=set_key;enh<='1';enm<='0'; ens<='0';
else cp<='0';enm<='0';enh<='0';ens<='0';
end if;
end process p1;

u1:second port map(clk_1Hz =>cp ,enable=>ens,s_low=>sl,s_high=>sh,count=>c1);
u2:minute port map(clk_1Hz =>cp ,enable=>enm,m_low=>ml,m_high=>mh,count=>c2);
u3:hour port map(clk_1Hz =>cp ,enable=>enh,h_low=>hl,h_high=>hh);
bell_h1<=hl;bell_h2<=hh;bell_m1<=ml;bell_m2<=mh;bell_s1<=sl;bell_s2<=sh;
end;