bcd7.vhd

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;

entity bcd7 is
port(
	date:in std_logic_vector(3 downto 0);
	a,b,c,d,e,f,g:out std_logic);
end bcd7;

architecture behave of bcd7 is
signal bcd7out:std_logic_vector(6 downto 0);

begin

	with date select
		bcd7out	<=
		"1111110" when "0000",
		"0110000" when "0001",
		"1101101" when "0010",
		"1111001" when "0011",
		"0110011" when "0100",
		"1011011" when "0101",
		"1011111" when "0110",
		"1110000" when "0111",
		"1111111" when "1000",
		"1111011" when "1001",
		"0000001" when "1010",
		"0000000" when others;

	a<=bcd7out(6);
	b<=bcd7out(5);
	c<=bcd7out(4);
	d<=bcd7out(3);
	e<=bcd7out(2);
	f<=bcd7out(1);
	g<=bcd7out(0);

end behave;