exit_reg.vhd

来自「Divisor do Tipo com restaura莽茫o sequenci」· VHDL 代码 · 共 31 行

library divisor ;
use divisor.pkg_divisor.ALL ;

entity exit_reg is
    Port ( qs : in  bit_vector ( (bit_width - 1) downto 0);
            q : out bit_vector ( (bit_width - 1) downto 0);
       ck,ld2 : in  bit ) ;
end exit_reg;

architecture Behavioral of exit_reg is
signal flag : boolean := false ;
begin

	control : process (ck,ld2,qs ) 
	begin

       if ld2 = '1' then    
		   if ( ck'event and ck='1')  then 
		  	   flag <= true ;
			end if ;
		 end if ;
		
	end process control ; 

q <= qs when flag = true else 
     ( OTHERS => '0' ) ;    
   

end Behavioral;