x_blk.vhd

来自「Divisor do Tipo com restaura莽茫o sequenci」· VHDL 代码 · 共 26 行

library divisor ;
use divisor.pkg_divisor.ALL ;


entity x_blk is

       PORT ( bi, ci, ri, qi : in bit ;
			            ri1,ci1 : out bit ) ;
		 
end x_blk ;

architecture Behavioral of x_blk is
signal s : bit ;
begin

  SUM : soma PORT MAP ( a => ri, b => bi,
                       ve => ci, vs => ci1, 
							   s => s ) ;

   
  ri1 <= s when qi = '1' else
         ri ;
         
end Behavioral;