somador.vhd

来自「Divisor do Tipo com restaura莽茫o sequenci」· VHDL 代码 · 共 14 行

entity soma is
   PORT ( a, b, ve : in bit ;
	          s, vs : out bit ) ;
end soma;

architecture Behavioral of soma is

begin
  s  <= a XOR b XOR ve ;
  vs <= ( a AND b ) or ( a AND ve ) or ( b AND ve ) ; 

end Behavioral;