📄 __model_tech_.._unisim__info
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tExplicit 1 GenerateLoopIterationMax 100000EbufgsrDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L125762VPno9Ge2;oRK_BNKnEl=BP0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Abufgsr_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgsr Pno9Ge2;oRK_BNKnEl=BP0OL;C;6.2b;3531M1 ieee std_logic_1164l125771L125770VHRHn@2DZzh4C3`k<]X:HN2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000EbufgtsDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L125799Vi[l2:Xa>YV_k7Sa5<3gbV1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Abufgts_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufgts i[l2:Xa>YV_k7Sa5<3gbV1OL;C;6.2b;3531M1 ieee std_logic_1164l125808L125807VJE@KHVdnSo=A50;GBMRYR1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000EbufioDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L131948V]_:nGjS`O?5<5kblB0VEB3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Abufio_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufio ]_:nGjS`O?5<5kblB0VEB3OL;C;6.2b;3531M1 ieee std_logic_1164l131958L131957VX6fngVl1lLJ`T51E=0]En0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000EbufrDP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg XYZ3Z9k?[fGmdXVMS_n7D0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L131994Vjf157Se=]OEY^mT]H?LzI2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Abufr_vw0DP ieee vital_primitives E9g6AWKAc2T]enMfl94If3DP ieee vital_timing OBWK>;kUYmkG<OChK2lhV1DP std textio K]Z^fghZ6B=BjnK5NomDT3DP unisim vpkg XYZ3Z9k?[fGmdXVMS_n7D0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work bufr jf157Se=]OEY^mT]H?LzI2OL;C;6.2b;3531M5 ieee std_logic_1164M4 unisim vpkgM3 std textioM2 ieee vital_timingM1 ieee vital_primitivesl132040L132012V8R`6Wb4;X@27mbg[<G^4j2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000EbuftDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1589VLXI@zkU>?5zHlH`oE?DdL1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Abuft_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work buft LXI@zkU>?5zHlH`oE?DdL1OL;C;6.2b;3531M1 ieee std_logic_1164l1599L1598VAEEOZ05YFNB1TKjY_3o=K2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_fpgacoreDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1650V6Bbh_>RNeBbgja_FTjo8j3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_fpgacore_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_fpgacore 6Bbh_>RNeBbgja_FTjo8j3OL;C;6.2b;3531M1 ieee std_logic_1164l1661L1660VUZRSQkl[;d9za2]9MQ6<C0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_spartan2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1691VD>fQYLegG0b91fCeKbXZg3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_spartan2_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_spartan2 D>fQYLegG0b91fCeKbXZg3OL;C;6.2b;3531M1 ieee std_logic_1164l1702L1701V4E0<;=1S9M_nTfUASA7ee1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_spartan3DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1732VQh^N?Z`NeKRk5Xz]ekbm^2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_spartan3_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_spartan3 Qh^N?Z`NeKRk5Xz]ekbm^2OL;C;6.2b;3531M1 ieee std_logic_1164l1743L1742Vd=gmSf`T6GKe_Y3KD>PA=2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_virtexDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1774VFezgkT3P?`cjgSlemgEd72OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_virtex_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex FezgkT3P?`cjgSlemgEd72OL;C;6.2b;3531M1 ieee std_logic_1164l1785L1784VhcmIZ4BJ17PHod1;Y3cz`2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_virtex2DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L1816VmTIXMYo;WdL3a1RKVHnS03OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_virtex2_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex2 mTIXMYo;WdL3a1RKVHnS03OL;C;6.2b;3531M1 ieee std_logic_1164l1827L1826VQ5@Oz_4dB:f9<29]NF4=I3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Ecapture_virtex4DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L132255V;T631hfYnTH9QFhGeJdY]1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Acapture_virtex4_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work capture_virtex4 ;T631hfYnTH9QFhGeJdY]1OL;C;6.2b;3531M1 ieee std_logic_1164l132268L132266V]5_9YZX3d9ZNf^BazgT2H1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div10DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L125836V;U1K^bS@2SIDVoS`>gdMB3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div10_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10 ;U1K^bS@2SIDVoS`>gdMB3OL;C;6.2b;3531M1 ieee std_logic_1164l125852L125848VTaULdG;3:0N@6f31KfY1I3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div10rDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L125896VJ:IeCgY?9;<7]b2Y`<9^l1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div10r_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10r J:IeCgY?9;<7]b2Y`<9^l1OL;C;6.2b;3531M1 ieee std_logic_1164l125914L125909V34O0Lc3KZ[IbN`Y56S_mf2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div10rsdDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126001V;51MBl`cGD@7]YIL4UA0>2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div10rsd_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10rsd ;51MBl`cGD@7]YIL4UA0>2OL;C;6.2b;3531M1 ieee std_logic_1164l126019L126014V=Q>RiK?n5K2f]?jKV4gSf3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div10sdDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126112VSDDh=ZXcH3ROYnb8WM>W=1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div10sd_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div10sd SDDh=ZXcH3ROYnb8WM>W=1OL;C;6.2b;3531M1 ieee std_logic_1164l126129L126125V=iPdLf1bHPZh]YZao4dP]0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div12DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126185Vz:8U>Zci;fV7gDGVHb:g@0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div12_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12 z:8U>Zci;fV7gDGVHb:g@0OL;C;6.2b;3531M1 ieee std_logic_1164l126200L126196ViSB5[BhU0cTifMBKAG[BS2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div12rDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126243VJSzS__@JzRKZ]hjPN=M4B3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div12r_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12r JSzS__@JzRKZ]hjPN=M4B3OL;C;6.2b;3531M1 ieee std_logic_1164l126261L126256VVKI6nXJ39h3loZag_D7AE0OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div12rsdDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126348VMoXkQGl]XKn:1^1bjVR@_1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div12rsd_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12rsd MoXkQGl]XKn:1^1bjVR@_1OL;C;6.2b;3531M1 ieee std_logic_1164l126366L126361VNEZQkDKPJ0FRo1hmnKe811OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div12sdDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126459VYbHcQV__AZQP=I[]XmHdO1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div12sd_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div12sd YbHcQV__AZQP=I[]XmHdO1OL;C;6.2b;3531M1 ieee std_logic_1164l126475L126471VjD49ZjbD=R_e9^GMfa_]V2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div14DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126530VEf[;DdVnX8T;E0Ll:LJiO3OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div14_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div14 Ef[;DdVnX8T;E0Ll:LJiO3OL;C;6.2b;3531M1 ieee std_logic_1164l126545L126541VGgDfTNB3TYg`?;ZWlzoDY1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div14rDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126589VWL6XVm1SR=_@69?n@8j0d1OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Aclk_div14r_vw0DP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2DE work clk_div14r WL6XVm1SR=_@69?n@8j0d1OL;C;6.2b;3531M1 ieee std_logic_1164l126606L126601Vn3kJk9kXPUY?^Z]H<04YU2OX;C;6.0d;29o-source -93 -work C:\MXE_LIBS\unmarked\expanded\unisim -O0tExplicit 1 GenerateLoopIterationMax 100000Eclk_div14rsdDP ieee std_logic_1164 GH1=`jDDBJ=`LM;:Ak`kf2OL;C;6.2b;3531w1142460874FC:\Xilinx\vhdl\src\unisims\unisim_VITAL.vhdl0L126693VA?PN[[f_>0`S@o60Kf[]j2⌨️ 快捷键说明
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