mem_interface_top_phy_dqs_iob.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_phy_dqs_iob.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module places the data stobes in the IOBs.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_phy_dqs_iob
  (
   input        clk0,
   input        clk90,
   input        rst0,
   input        dlyinc_dqs,
   input        dlyce_dqs,
   input        dlyrst_dqs,
   input        dqs_oe_n,
   input        dqs_rst_n,
   inout        ddr_dqs,
   inout        ddr_dqs_n,
   output       delayed_dqs
   );

  wire          clk180;
  wire          dqs_ibuf_n;
  wire          dqs_idelay;
  wire          dqs_oe_n_r;
  wire          dqs_out;
  wire          i_dqs_gated;
  reg           dqs_rst_n_r /* synthesis syn_maxfan = 1 */
                /* synthesis syn_preserve=1 */;


  assign        clk180 = ~clk0;

  //***************************************************************************
  // DQS input-side resources
  //***************************************************************************

  IODELAY #
    (
     .DELAY_SRC("I"),
     .HIGH_PERFORMANCE_MODE("TRUE"),
     .IDELAY_TYPE("VARIABLE"),
     .IDELAY_VALUE(0),
     .ODELAY_VALUE(0)
     )
    u_idelay_dqs
      (
       .DATAOUT (dqs_idelay),
       .C       (clk90),
       .CE      (dlyce_dqs),
       .DATAIN  (),
       .IDATAIN (dqs_ibuf_n),
       .INC     (dlyinc_dqs),
       .ODATAIN (),
       .RST     (dlyrst_dqs),
       .T       ()
       );

  BUFIO u_bufio_dqs
    (
     .I  (dqs_idelay),
     .O  (i_dqs_gated)
     );

  // Temporary - to model additional delay of DQS BUFIO + gating network
  // for behavioral simulation. Make sure to select a delay number smaller
  // than half clock cycle (otherwise output will not track input changes
  // because of inertial delay)
  assign #(0.8) delayed_dqs = i_dqs_gated;

  // synthesis attribute max_fanout of dqs_rst_n_r is 1
  // synthesis attribute equivalent_register_removal of dqs_rst_n_r is "no";
   always @(posedge clk180)
    dqs_rst_n_r <= dqs_rst_n;

  ODDR #
    (
     .SRTYPE("SYNC"),
     .DDR_CLK_EDGE("OPPOSITE_EDGE")
     )
    u_oddr_dqs
      (
       .Q  (dqs_out),
       .C  (clk180),
       .CE (1'b1),
       .D1 (dqs_rst_n_r),
       .D2 (1'b0),
       .R  (1'b0),
       .S  (1'b0)
       );

  (* IOB = "TRUE" *) FDP u_tri_state_dqs
    (
     .D   (dqs_oe_n),
     .Q   (dqs_oe_n_r),
     .C   (clk180),
     .PRE (rst0)
     ) /* synthesis syn_useioff = 1 */;

  //***************************************************************************

  IOBUFDS iobuf_dqs
    (
     .O   (dqs_ibuf_n),
     .IO  (ddr_dqs),
     .IOB (ddr_dqs_n),
     .I   (dqs_out),
     .T   (dqs_oe_n_r)
     );



endmodule