mem_interface_top_phy_dm_iob.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_phy_dm_iob.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 16 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module places the data mask signals into the IOBs.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_phy_dm_iob
  (
   input  clk90,
   input  mask_data_rise,
   input  mask_data_fall,
   output ddr_dm
   );

  wire    dm_out;

  ODDR #
    (
     .SRTYPE("SYNC"),
     .DDR_CLK_EDGE("SAME_EDGE")
     )
    u_oddr_dm
      (
       .Q  (dm_out),
       .C  (clk90),
       .CE (1'b1),
       .D1 (mask_data_rise),
       .D2 (mask_data_fall),
       .R  (1'b0),
       .S  (1'b0)
       );

  OBUF u_obuf_dm
    (
     .I (dm_out),
     .O (ddr_dm)
     );

endmodule