mem_interface_top_usr_rd_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_rd_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Tue Aug 29 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   The delay between the read data with respect to the command issued is
//   calculted in terms of no. of clocks. This data is then stored into the
//   FIFOs and then read back and given as the ouput for comparison.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_rd_0 #
  (
   parameter DQ_WIDTH      = 72,
   parameter DQ_PER_DQS    = 8,
   parameter DQS_WIDTH     = 9
   )
  (
   input                                    clk,
   input                                    rst,
   input [DQ_WIDTH-1:0]                     rd_data_in_rise,
   input [DQ_WIDTH-1:0]                     rd_data_in_fall,
   input [DQS_WIDTH-1:0]                    ctrl_rden,
   output                                   rd_data_valid,
   output [DQ_WIDTH-1:0]                    rd_data_out_rise,
   output [DQ_WIDTH-1:0]                    rd_data_out_fall
   );

  reg                  fifo_rden_r0;
  reg                  fifo_rden_r1;
  reg                  fifo_rden_r2;
  reg                  fifo_rden_r3;
  wire [DQS_WIDTH-1:0] i_rd_data_valid;

  //***************************************************************************

  // can use any of the read valids, they're all delayed by same amount
  assign rd_data_valid = i_rd_data_valid[0];

  // delay read valid to take into account maximum delay difference between
  // the read enable coming from the different DQS groups
  always @(posedge clk) begin
    if (rst) begin
      fifo_rden_r0 <= 1'b0;
      fifo_rden_r1 <= 1'b0;
      fifo_rden_r2 <= 1'b0;
      fifo_rden_r3 <= 1'b0;
    end else begin
      fifo_rden_r0 <= ctrl_rden[0];
      fifo_rden_r1 <= fifo_rden_r0;
      fifo_rden_r2 <= fifo_rden_r1;
      fifo_rden_r3 <= fifo_rden_r2;
    end
  end

  genvar fifo_i;
  generate
    for(fifo_i = 0; fifo_i < DQS_WIDTH; fifo_i = fifo_i+1) begin: gen_fifo
      mem_interface_top_usr_rd_fifo_0 #
        (
         .DATA_WIDTH (DQ_PER_DQS)
         )
        u_rd_fifo
        (
         .clk           (clk),
         .rst           (rst),
         .rden          (fifo_rden_r3),
         .wren          (ctrl_rden[fifo_i]),
         .data_in_rise  (rd_data_in_rise[DQ_PER_DQS*(fifo_i+1)-1:
                                         DQ_PER_DQS*fifo_i]),
         .data_in_fall  (rd_data_in_fall[DQ_PER_DQS*(fifo_i+1)-1:
                                         DQ_PER_DQS*fifo_i]),
         .data_valid    (i_rd_data_valid[fifo_i]),
         .data_out_rise (rd_data_out_rise[DQ_PER_DQS*(fifo_i+1)-1:
                                          DQ_PER_DQS*fifo_i]),
         .data_out_fall (rd_data_out_fall[DQ_PER_DQS*(fifo_i+1)-1:
                                          DQ_PER_DQS*fifo_i])
         );
    end
  endgenerate

endmodule