mem_interface_top_usr_rd_fifo_0.v

sata_device_model,对做硬盘控制器的朋友有帮助

//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_rd_fifo_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Wed Aug 30 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//  This module instantiates the distributed RAM which stores the read data
//  from the memory. This module is configured as a synchronous, First-Word-
//  Fall-Through 16-deep FIFO.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_rd_fifo_0 #
  (
   parameter DATA_WIDTH = 72
   )
  (
   input                   clk,
   input                   rst,
   input                   wren,
   input                   rden,
   input [DATA_WIDTH-1:0]  data_in_rise,
   input [DATA_WIDTH-1:0]  data_in_fall,
   output                  data_valid,
   output [DATA_WIDTH-1:0] data_out_rise,
   output [DATA_WIDTH-1:0] data_out_fall
   );

  wire [DATA_WIDTH-1:0]    dout_fall;
  reg [DATA_WIDTH-1:0]     dout_fall_r;
  wire [DATA_WIDTH-1:0]    dout_rise;
  reg [DATA_WIDTH-1:0]     dout_rise_r;
  reg [3:0]                rd_addr;
  reg                      rden_r /* synthesis syn_preserve=1 */;
  reg [3:0]                wr_addr;

  //***************************************************************************

  assign data_valid    = rden_r;
  assign data_out_fall = dout_fall_r;
  assign data_out_rise = dout_rise_r;

  //***************************************************************************
  // Read Data Valid generation for fifos based on write enable
  //***************************************************************************

  // synthesis attribute equivalent_register_removal of rden_r is "no";
  always @(posedge clk)
    if (rst)
      rden_r <= 1'b0;
    else
      rden_r <= rden;

  //***************************************************************************
  // Write Pointer increment for FIFOs
  //***************************************************************************

  always @(posedge clk)
    if (rst)
      wr_addr <= 'h0;
    else if (wren)
      wr_addr <= wr_addr + 1;

  //***************************************************************************
  // Read Pointer and fifo data output sequencing
  //***************************************************************************

  always @(posedge clk)
    if (rst)
      rd_addr <= 'h0;
    else if (rden)
      rd_addr <= rd_addr + 1;

  // pipelining of read data
  always @(posedge clk) begin
    dout_rise_r <= dout_rise;
    dout_fall_r <= dout_fall;
  end

  //***************************************************************************
  // Distributed RAM 4 bit wide FIFO instantiations (2 FIFOs per strobe,
  // rising edge data fifo and falling edge data fifo)
  //***************************************************************************

  mem_interface_top_usr_ram_d_0 #
    (
     .DATA_WIDTH (DATA_WIDTH)
     )
    u_usr_ram_rise
    (
     .addra    (wr_addr),
     .addrb    (rd_addr),
     .clka     (clk),
     .wea      (wren),
     .dinb     (data_in_rise),
     .douta    (dout_rise)
     );

  mem_interface_top_usr_ram_d_0 #
    (
     .DATA_WIDTH (DATA_WIDTH)
     )
    u_usr_ram_fall
    (
     .addra    (wr_addr),
     .addrb    (rd_addr),
     .clka     (clk),
     .wea      (wren),
     .dinb     (data_in_fall),
     .douta    (dout_fall)
     );

endmodule