shdd_model.v

sata_device_model,对做硬盘控制器的朋友有帮助

        .TILE0_RXCLKCORCNT0_OUT         (),
        .TILE0_RXCLKCORCNT1_OUT         (),
        //------------- Receive Ports - Comma Detection and Alignment --------------
        .TILE0_RXBYTEISALIGNED0_OUT     (),
        .TILE0_RXBYTEISALIGNED1_OUT     (),
        .TILE0_RXENMCOMMAALIGN0_IN      (1'b1),
        .TILE0_RXENMCOMMAALIGN1_IN      (1'b1),
        .TILE0_RXENPCOMMAALIGN0_IN      (1'b1),
        .TILE0_RXENPCOMMAALIGN1_IN      (1'b1),
        //----------------- Receive Ports - RX Data Path interface -----------------
        .TILE0_RXDATA0_OUT              (tile0_rxdata0_out),
        .TILE0_RXDATA1_OUT              (),
        .TILE0_RXRESET0_IN              (!refclkout_dcm0_locked_i),
        .TILE0_RXRESET1_IN              (!refclkout_dcm0_locked_i),
        .TILE0_RXUSRCLK0_IN             (tile0_txusrclk0_i),
        .TILE0_RXUSRCLK1_IN             (tile0_txusrclk0_i),
        .TILE0_RXUSRCLK20_IN            (tile0_txusrclk20_i),
        .TILE0_RXUSRCLK21_IN            (tile0_txusrclk20_i),
        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        .TILE0_RXELECIDLE0_OUT          (rxelecidle0),
        .TILE0_RXELECIDLE1_OUT          (),
        .TILE0_RXN0_IN                  (RXN_IN0),
        .TILE0_RXN1_IN                  (),
        .TILE0_RXP0_IN                  (RXP_IN0),
        .TILE0_RXP1_IN                  (),
        //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        .TILE0_RXSTATUS0_OUT            (tile0_rxstatus0_i),
        .TILE0_RXSTATUS1_OUT            (),
        //------------- Receive Ports - RX Loss-of-sync State Machine --------------
        .TILE0_RXLOSSOFSYNC0_OUT        (),
        .TILE0_RXLOSSOFSYNC1_OUT        (),    
        //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
        .TILE0_DADDR_IN                 (7'h0),//(daddr),
        .TILE0_DCLK_IN                  (1'b0),//(tile0_refclkout_i),
        .TILE0_DEN_IN                   (1'b0),//(den),
        .TILE0_DI_IN                    (16'h0),//(di),
        .TILE0_DO_OUT                   (),//(do),
        .TILE0_DRDY_OUT                 (),//(drdy),
        .TILE0_DWE_IN                   (1'b0),//(dwe),
            
        //------------------- Shared Ports - Tile and PLL Ports --------------------
        .TILE0_CLKIN_IN                 (tile0_refclk_i),
        .TILE0_GTPRESET_IN              (!globol_reset_n),
        .TILE0_PLLLKDET_OUT             (tile0_plllkdet_i),
        .TILE0_REFCLKOUT_OUT            (tile0_refclkout_i),
        .TILE0_RESETDONE0_OUT           (tile0_resetdone0_i),
        .TILE0_RESETDONE1_OUT           (),
        //.TILE0_TXENPMAPHASEALIGN_IN     (txenpmaphasealign_i),
        //.TILE0_TXPMASETPHASE_IN         (txpmasetphase_i),
        
        //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
        .TILE0_TXCHARISK0_IN            (tile0_txcharisk0_in),
        .TILE0_TXCHARISK1_IN            (),
        //---------------- Transmit Ports - TX Data Path interface -----------------
        .TILE0_TXDATA0_IN               (tile0_txdata0_in),
        .TILE0_TXDATA1_IN               (),
        .TILE0_TXRESET0_IN              (!refclkout_dcm0_locked_i),
        .TILE0_TXRESET1_IN              (!refclkout_dcm0_locked_i),
        .TILE0_TXUSRCLK0_IN             (tile0_txusrclk0_i),
        .TILE0_TXUSRCLK1_IN             (tile0_txusrclk0_i),
        .TILE0_TXUSRCLK20_IN            (tile0_txusrclk20_i),
        .TILE0_TXUSRCLK21_IN            (tile0_txusrclk20_i),
        //------------- Transmit Ports - TX Driver and OOB signalling --------------
        .TILE0_TXDIFFCTRL0_IN           (3'b0),
        .TILE0_TXDIFFCTRL1_IN           (3'b0),
        .TILE0_TXN0_OUT                 (TXN_OUT0),
        .TILE0_TXN1_OUT                 (),
        .TILE0_TXP0_OUT                 (TXP_OUT0),
        .TILE0_TXP1_OUT                 (),
        .TILE0_TXPREEMPHASIS0_IN        (3'h0),
        .TILE0_TXPREEMPHASIS1_IN        (3'h0),

        .TILE0_TXELECIDLE0_IN(txelecidle0),
        .TILE0_TXELECIDLE1_IN(),
        
        //------------------- Transmit Ports - TX Ports for SATA -------------------
        .TILE0_TXCOMSTART0_IN           (tx_comreset0|tx_comwake0),
        .TILE0_TXCOMSTART1_IN           (1'b0),
        .TILE0_TXCOMTYPE0_IN            (tx_comwake0),
        .TILE0_TXCOMTYPE1_IN            (1'b0)


    ); 
   

ddr2_sodimm ddr2_sodimm_inst (
                .clk0(clk0), 
                .clk0_n(clk0_n), 
                .clk1(clk1), 
                .clk1_n(clk1_n), 
                .cke(cke), 
                .cs_n(cs_n), 
                .ras_n(ras_n), 
                .cas_n(cas_n), 
                .we_n(we_n), 
                .dm_rdqs(dm_rdqs[7:0]), 
                .s_n(cs_n), 
                .ba({1'b0,ba[1:0]}), 
                .a(a[12:0]), 
                .dq(dq), 
                .dqs(dqs), 
                .dqs_n(dqs_n), 
                .rdqs_n(), 
                .odt(odt)
        );    
mem_interface_top #(
       .BANK_WIDTH(2),       
       .CLK_WIDTH(2),
       .DM_WIDTH(8),      
       .DQ_WIDTH(64),    
       .DQS_WIDTH(8),      
       .ROW_WIDTH(13),      
       .CAS_LAT(4),      
       .REG_ENABLE(0),
       .SIM_ONLY(DDR_SIM)     
    )
    ddr2_cntrl_inst(
       .ddr2_dq          (dq),                      //inout  [63:0]  
       .ddr2_a           (a),                       //output  [13:0]  
       .ddr2_ba          (ba),                      //output  [1:0]  
       .ddr2_ras_n       (ras_n),                   //output  
       .ddr2_cas_n       (cas_n),                   //output  
       .ddr2_we_n        (we_n),                    //output  
       .ddr2_reset_n     (),                 //output  
       .ddr2_cs_n        (cs_n),                    //output  [0:0]  
       .ddr2_odt         (odt),                     //output  [0:0]  
       .ddr2_cke         (cke),                     //output  [0:0]  
       .ddr2_dm          (dm_rdqs),                      //output  [8:0]  
       .sys_clk_p        (ddr_clk_p),                    //input  
       .sys_clk_n        (ddr_clk_n),                    //input  
       .clk200_p         (ddr_clk_p),                     //input  
       .clk200_n         (ddr_clk_n),                     //input  
       .sys_rst_n        (globol_reset_n),                //input 
       .rst0_tb          (rst0_tb),        //output 
       .clk0_tb          (clk0_tb),      //output 
       .phy_init_done    (phy_init_done), //output  
       .app_wdf_afull    (write_data_full),              //output  
       .app_af_afull     (addr_almost_full),             //output  
       .rd_data_valid    (read_mem_valid),               //output  
       .app_wdf_wren     (data_wren),                    //input  
       .app_af_wren      (addr_wren),                    //input  
       .app_af_addr      (mem_addr[30:0]),               //input  [30:0]  
       .app_af_cmd       (mem_cmd),
       .rd_data_fifo_out (read_mem_data),                 
       .app_wdf_data     (write_mem_data),  
       .app_wdf_mask_data(16'h0),                        //input  [15:0]  
       .ddr2_dqs         (dqs),                     //inout  [7:0]  
       .ddr2_dqs_n       (dqs_n),                   //inout  [7:0]  
       .ddr2_ck          ({clk1,clk0}),                      //output  [1:0]  
       .ddr2_ck_n        ({clk0_n,clk1_n})                     //output  [1:0]  
    );
   dma_ddr2_if dma_ddr2_if_inst(
       .dma_clk             (tile0_refclkout_i),
       .ddr_clk             (clk0_tb),
       .reset               (rst0_tb),

       //egress
       .egress_data         (egress_data),
       .egress_fifo_rd      (egress_fifo_rd),      
       .egress_fifo_status  (egress_fifo_status),  
       .egress_xfer_size    (egress_xfer_size),
       .egress_start_addr   (egress_start_addr),
       .egress_data_req     (egress_data_req),
       .egress_data_ack     (egress_data_ack),
       
       //ingress
       .ingress_data        (ingress_data),
       .ingress_fifo_wr     (ingress_fifo_wr),     
       .ingress_fifo_status (ingress_fifo_status), 
       .ingress_xfer_size   (ingress_xfer_size),
       .ingress_start_addr  (ingress_start_addr),
       .ingress_data_req    (ingress_data_req),
       .ingress_data_ack    (ingress_data_ack),
       //END OF DMA SIGNALS

       //MEMORY CNTRLR SIGNALS
       .m_wrdata_temp            (write_mem_data),
       .m_addr_temp              (mem_addr),
       .m_cmd_temp               (mem_cmd),
       .m_data_wen_temp          (data_wren),
       .m_addr_wen_temp          (addr_wren),
       .m_rddata            (read_mem_data),       
       .m_af_afull          (addr_almost_full),
       .m_wdf_afull         (write_data_full),
       .m_data_valid        (read_mem_valid)
       //END OF MEMORY CNTRLR SIGNALS
    );
endmodule