shdd_model.v

sata_device_model,对做硬盘控制器的朋友有帮助

module shdd_model(

  globol_reset_n,

  TXN_OUT0,
  TXP_OUT0,
  RXN_IN0,
  RXP_IN0,
  sata_clk_n,
  sata_clk_p,

  
  ddr_clk_p,
  ddr_clk_n
  

                 );
parameter EXAMPLE_SIM_GTPRESET_SPEEDUP              =   1;   // simulation setting for MGT smartmodel
parameter EXAMPLE_SIM_PLL_PERDIV2                   =   9'h14d; // simulation setting for MGT smartmodel
parameter DDR_SIM=1;
parameter EXAMPLE_SIM_MODE                          =   "FAST";  // Set to Fast Functional Simulation Model   

input  globol_reset_n;

output TXN_OUT0;
output TXP_OUT0;
input  RXN_IN0;
input  RXP_IN0;
input  sata_clk_n;
input  sata_clk_p;

input  ddr_clk_p;
input  ddr_clk_n;



wire  [127:0] write_mem_data;
wire  [31:0]  mem_addr;
wire  [2:0]   mem_cmd;
wire          data_wren,addr_wren;
wire [127:0]  read_mem_data;
wire          write_data_full,addr_almost_full,read_mem_valid,rst0_tb,clk0_tb;

wire tile0_refclkout_i,pcie0_plllkdet_i,tile0_txusrclk0_i,tile0_txusrclk20_i,refclkout_dcm0_locked_i,
tile0_refclkout_to_dcm_i,refclkout_dcm0_reset_i,TILE0_PLLLKDET_OUT,tile0_plllkdet_i,tile0_gtpreset_i,resetdone0;
wire tile0_refclk_i,rxelecidle0,tx_comreset0,tx_comwake0,txelecidle0,tile0_rxelecidle0_out,tile0_resetdone0_i;
wire [1:0]tile0_rxchariscomma0_out,tile0_rxlossofsync0_i,tile0_rxcharisk0_out,tile0_rxdisperr0_out,tile0_rxnotintable0_out,tile0_txcharisk0_in;
wire [2:0] tile0_rxstatus0_i,tile0_loopback0_in;
wire  [15:0]  tile0_rxdata0_out,tile0_txdata0_in;
wire clk0;
wire clk0_n;
wire clk1;
wire clk1_n;
wire cke;
wire cs_n;
wire ras_n;
wire cas_n;
wire we_n;
wire s_n;
wire [1:0] ba;
wire [12:0] a;
wire odt;
wire rdqs_n;
wire [7:0] dm_rdqs;
wire [63:0] dq;
wire [7:0] dqs;
wire [7:0] dqs_n;
wire  [31:0]    egress_data;
wire    [2:0]   egress_fifo_status;   
wire            egress_data_ack;
wire     [2:0] egress_xfer_size;
wire    [31:0] egress_start_addr;
wire           egress_data_req;
wire           egress_fifo_rd;    
wire            ingress_data_ack;
wire    [1:0]   ingress_fifo_status; 
wire   [31:0]  ingress_data;
wire           ingress_fifo_wr;   
wire     [2:0] ingress_xfer_size;
wire    [31:0] ingress_start_addr;
wire           ingress_data_req;
wire dclk;
wire txenpmaphasealign_i,txpmasetphase_i;
reg             tile0_resetdone0_r2,tile0_resetdone0_r,calibrated;


sata_hdd sata_hdd(
                .globol_reset_n(globol_reset_n) ,
                

       //egress
       .egress_data         (egress_data),
       .egress_fifo_rd      (egress_fifo_rd),      
       .egress_fifo_status  (egress_fifo_status),  
       .egress_xfer_size    (egress_xfer_size),
       .egress_start_addr   (egress_start_addr),
       .egress_data_req     (egress_data_req),
       .egress_data_ack     (egress_data_ack),
       
       //ingress
       .ingress_data        (ingress_data),
       .ingress_fifo_wr     (ingress_fifo_wr),     
       .ingress_fifo_status (ingress_fifo_status), 
       .ingress_xfer_size   (ingress_xfer_size),
       .ingress_start_addr  (ingress_start_addr),
       .ingress_data_req    (ingress_data_req),
       .ingress_data_ack    (ingress_data_ack),
                
                .tile0_txusrclk20_i(tile0_txusrclk20_i),
                .tile0_refclkout_i(tile0_refclkout_i),
                .tile0_rxstatus0_i(tile0_rxstatus0_i),
                .tile0_rxchariscomma0_out(tile0_rxchariscomma0_out),
                .tile0_rxcharisk0_out(tile0_rxcharisk0_out),
                .tile0_rxdisperr0_out(tile0_rxdisperr0_out),
                .tile0_rxnotintable0_out(tile0_rxnotintable0_out),
                .tile0_resetdone0_i(tile0_resetdone0_i),
                .tile0_rxelecidle0_out(rxelecidle0),
                .tile0_rxdata0_out(tile0_rxdata0_out),
                .tx_comreset(tx_comreset0),
                .tx_comwake(tx_comwake0),
                .txelecidle(txelecidle0),
                .tile0_loopback0_in(tile0_loopback0_in),
                .tile0_txdata0_in(tile0_txdata0_in),
                .tile0_txcharisk0_in(tile0_txcharisk0_in)
   
 );


//SATA GTP
    IBUFDS tile0_refclk_ibufds_i
    (
        .O                              (tile0_refclk_i), 
        .I                              (sata_clk_p),
        .IB                             (sata_clk_n)
    );




    BUFG refclkout_dcm0_bufg_i
    (
        .I                              (tile0_refclkout_i),
        .O                              (tile0_refclkout_to_dcm_i)
    );

    assign  refclkout_dcm0_reset_i          =  !tile0_plllkdet_i;
    MGT_USRCLK_SOURCE #
    (
        .FREQUENCY_MODE                 ("LOW"),
        .PERFORMANCE_MODE               ("MAX_SPEED")
    )
    refclkout_dcm0_i
    (
        .DIV1_OUT                       (tile0_txusrclk0_i),
        .DIV2_OUT                       (tile0_txusrclk20_i),
        .DCM_LOCKED_OUT                 (refclkout_dcm0_locked_i),
        .CLK_IN                         (tile0_refclkout_to_dcm_i),
        .DCM_RESET_IN                   (refclkout_dcm0_reset_i)
    );

    


    SATA_GTP #
    (
        //.WRAPPER_SIM_MODE                       (EXAMPLE_SIM_MODE),    
        .WRAPPER_SIM_GTPRESET_SPEEDUP           (EXAMPLE_SIM_GTPRESET_SPEEDUP),
        .WRAPPER_SIM_PLL_PERDIV2                (EXAMPLE_SIM_PLL_PERDIV2)
    )
    sata_gtp_i
    (
     
        //_____________________________________________________________________
        //_____________________________________________________________________
        //TILE0  (X0Y5)

        //---------------------- Loopback and Powerdown Ports ----------------------
        .TILE0_LOOPBACK0_IN             (tile0_loopback0_in),
        .TILE0_LOOPBACK1_IN             (),
        //--------------------- Receive Ports - 8b10b Decoder ----------------------
        .TILE0_RXCHARISCOMMA0_OUT       (tile0_rxchariscomma0_out),
        .TILE0_RXCHARISCOMMA1_OUT       (),
        .TILE0_RXCHARISK0_OUT           (tile0_rxcharisk0_out),
        .TILE0_RXCHARISK1_OUT           (),
        .TILE0_RXDISPERR0_OUT           (tile0_rxdisperr0_out),
        .TILE0_RXDISPERR1_OUT           (),
        .TILE0_RXNOTINTABLE0_OUT        (tile0_rxnotintable0_out),
        .TILE0_RXNOTINTABLE1_OUT        (),
        //----------------- Receive Ports - Clock Correction Ports -----------------