📄 sata_gtp_tile.v
字号:
.CHAN_BOND_SEQ_1_2_0 (10'b0000000000), .CHAN_BOND_SEQ_1_3_0 (10'b0000000000), .CHAN_BOND_SEQ_1_4_0 (10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE_0 (4'b0000), .CHAN_BOND_SEQ_2_1_0 (10'b0000000000), .CHAN_BOND_SEQ_2_2_0 (10'b0000000000), .CHAN_BOND_SEQ_2_3_0 (10'b0000000000), .CHAN_BOND_SEQ_2_4_0 (10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE_0 (4'b0000), .CHAN_BOND_SEQ_2_USE_0 ("FALSE"), .CHAN_BOND_SEQ_LEN_0 (1), .PCI_EXPRESS_MODE_0 ("FALSE"), .CHAN_BOND_1_MAX_SKEW_1 (7), .CHAN_BOND_2_MAX_SKEW_1 (7), .CHAN_BOND_LEVEL_1 (TILE_CHAN_BOND_LEVEL_1), .CHAN_BOND_MODE_1 (TILE_CHAN_BOND_MODE_1), .CHAN_BOND_SEQ_1_1_1 (10'b0000000000), .CHAN_BOND_SEQ_1_2_1 (10'b0000000000), .CHAN_BOND_SEQ_1_3_1 (10'b0000000000), .CHAN_BOND_SEQ_1_4_1 (10'b0000000000), .CHAN_BOND_SEQ_1_ENABLE_1 (4'b0000), .CHAN_BOND_SEQ_2_1_1 (10'b0000000000), .CHAN_BOND_SEQ_2_2_1 (10'b0000000000), .CHAN_BOND_SEQ_2_3_1 (10'b0000000000), .CHAN_BOND_SEQ_2_4_1 (10'b0000000000), .CHAN_BOND_SEQ_2_ENABLE_1 (4'b0000), .CHAN_BOND_SEQ_2_USE_1 ("FALSE"), .CHAN_BOND_SEQ_LEN_1 (1), .PCI_EXPRESS_MODE_1 ("FALSE"), //---------------- RX Attributes for PCI Express/SATA --------------- .RX_STATUS_FMT_0 ("SATA"), .SATA_BURST_VAL_0 (3'b100), .SATA_IDLE_VAL_0 (3'b100), .SATA_MAX_BURST_0 (7), .SATA_MAX_INIT_0 (22), .SATA_MAX_WAKE_0 (7), .SATA_MIN_BURST_0 (4), .SATA_MIN_INIT_0 (12), .SATA_MIN_WAKE_0 (4), .TRANS_TIME_FROM_P2_0 (16'h0060), .TRANS_TIME_NON_P2_0 (16'h0025), .TRANS_TIME_TO_P2_0 (16'h0100), .RX_STATUS_FMT_1 ("SATA"), .SATA_BURST_VAL_1 (3'b100), .SATA_IDLE_VAL_1 (3'b100), .SATA_MAX_BURST_1 (7), .SATA_MAX_INIT_1 (22), .SATA_MAX_WAKE_1 (7), .SATA_MIN_BURST_1 (4), .SATA_MIN_INIT_1 (12), .SATA_MIN_WAKE_1 (4), .TRANS_TIME_FROM_P2_1 (16'h0060), .TRANS_TIME_NON_P2_1 (16'h0025), .TRANS_TIME_TO_P2_1 (16'h0100) ) gtp_dual_i ( //---------------------- Loopback and Powerdown Ports ---------------------- .LOOPBACK0 (loopback0_i), .LOOPBACK1 (loopback1_i), .RXPOWERDOWN0 (tied_to_ground_vec_i[1:0]), .RXPOWERDOWN1 (tied_to_ground_vec_i[1:0]), .TXPOWERDOWN0 (tied_to_ground_vec_i[1:0]), .TXPOWERDOWN1 (tied_to_ground_vec_i[1:0]), //--------------------- Receive Ports - 8b10b Decoder ---------------------- .RXCHARISCOMMA0 (RXCHARISCOMMA0_OUT), .RXCHARISCOMMA1 (RXCHARISCOMMA1_OUT), .RXCHARISK0 (RXCHARISK0_OUT), .RXCHARISK1 (RXCHARISK1_OUT), .RXDEC8B10BUSE0 (tied_to_vcc_i), .RXDEC8B10BUSE1 (tied_to_vcc_i), .RXDISPERR0 (RXDISPERR0_OUT), .RXDISPERR1 (RXDISPERR1_OUT), .RXNOTINTABLE0 (RXNOTINTABLE0_OUT), .RXNOTINTABLE1 (RXNOTINTABLE1_OUT), .RXRUNDISP0 (), .RXRUNDISP1 (), //----------------- Receive Ports - Channel Bonding Ports ------------------ .RXCHANBONDSEQ0 (), .RXCHANBONDSEQ1 (), .RXCHBONDI0 (tied_to_ground_vec_i[2:0]), .RXCHBONDI1 (tied_to_ground_vec_i[2:0]), .RXCHBONDO0 (), .RXCHBONDO1 (), .RXENCHANSYNC0 (tied_to_ground_i), .RXENCHANSYNC1 (tied_to_ground_i), //----------------- Receive Ports - Clock Correction Ports ----------------- .RXCLKCORCNT0 (RXCLKCORCNT0_OUT), .RXCLKCORCNT1 (RXCLKCORCNT1_OUT), //------------- Receive Ports - Comma Detection and Alignment -------------- .RXBYTEISALIGNED0 (RXBYTEISALIGNED0_OUT), .RXBYTEISALIGNED1 (RXBYTEISALIGNED1_OUT), .RXBYTEREALIGN0 (), .RXBYTEREALIGN1 (), .RXCOMMADET0 (), .RXCOMMADET1 (), .RXCOMMADETUSE0 (tied_to_vcc_i), .RXCOMMADETUSE1 (tied_to_vcc_i), .RXENMCOMMAALIGN0 (RXENMCOMMAALIGN0_IN), .RXENMCOMMAALIGN1 (RXENMCOMMAALIGN1_IN), .RXENPCOMMAALIGN0 (RXENPCOMMAALIGN0_IN), .RXENPCOMMAALIGN1 (RXENPCOMMAALIGN1_IN), .RXSLIDE0 (tied_to_ground_i), .RXSLIDE1 (tied_to_ground_i), //--------------------- Receive Ports - PRBS Detection --------------------- .PRBSCNTRESET0 (tied_to_ground_i), .PRBSCNTRESET1 (tied_to_ground_i), .RXENPRBSTST0 (tied_to_ground_vec_i[1:0]), .RXENPRBSTST1 (tied_to_ground_vec_i[1:0]), .RXPRBSERR0 (), .RXPRBSERR1 (), //----------------- Receive Ports - RX Data Path interface ----------------- .RXDATA0 (rxdata0_i), .RXDATA1 (rxdata1_i), .RXDATAWIDTH0 (tied_to_vcc_i), .RXDATAWIDTH1 (tied_to_vcc_i), .RXRECCLK0 (), .RXRECCLK1 (), .RXRESET0 (RXRESET0_IN), .RXRESET1 (RXRESET1_IN), .RXUSRCLK0 (RXUSRCLK0_IN), .RXUSRCLK1 (RXUSRCLK1_IN), .RXUSRCLK20 (RXUSRCLK20_IN), .RXUSRCLK21 (RXUSRCLK21_IN), //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------ .RXCDRRESET0 (tied_to_ground_i), .RXCDRRESET1 (tied_to_ground_i), .RXELECIDLE0 (rxelecidle0_i), .RXELECIDLE1 (rxelecidle1_i), .RXELECIDLERESET0 (rxelecidlereset0_i), .RXELECIDLERESET1 (rxelecidlereset1_i), .RXENEQB0 (tied_to_vcc_i), .RXENEQB1 (tied_to_vcc_i), .RXEQMIX0 (tied_to_ground_vec_i[1:0]), .RXEQMIX1 (tied_to_ground_vec_i[1:0]), .RXEQPOLE0 (tied_to_ground_vec_i[3:0]), .RXEQPOLE1 (tied_to_ground_vec_i[3:0]), .RXN0 (RXN0_IN), .RXN1 (RXN1_IN), .RXP0 (RXP0_IN), .RXP1 (RXP1_IN), //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports ------- .RXBUFRESET0 (tied_to_ground_i), .RXBUFRESET1 (tied_to_ground_i), .RXBUFSTATUS0 (), .RXBUFSTATUS1 (), .RXCHANISALIGNED0 (), .RXCHANISALIGNED1 (), .RXCHANREALIGN0 (), .RXCHANREALIGN1 (), .RXPMASETPHASE0 (tied_to_ground_i), .RXPMASETPHASE1 (tied_to_ground_i), .RXSTATUS0 (RXSTATUS0_OUT), .RXSTATUS1 (RXSTATUS1_OUT), //------------- Receive Ports - RX Loss-of-sync State Machine -------------- .RXLOSSOFSYNC0 (RXLOSSOFSYNC0_OUT), .RXLOSSOFSYNC1 (RXLOSSOFSYNC1_OUT), //-------------------- Receive Ports - RX Oversampling --------------------- .RXENSAMPLEALIGN0 (tied_to_ground_i), .RXENSAMPLEALIGN1 (tied_to_ground_i), .RXOVERSAMPLEERR0 (), .RXOVERSAMPLEERR1 (), //------------ Receive Ports - RX Pipe Control for PCI Express ------------- .PHYSTATUS0 (), .PHYSTATUS1 (), .RXVALID0 (), .RXVALID1 (), //--------------- Receive Ports - RX Polarity Control Ports ---------------- .RXPOLARITY0 (tied_to_ground_i), .RXPOLARITY1 (tied_to_ground_i), //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------ .DADDR (DADDR_IN), .DCLK (DCLK_IN), .DEN (DEN_IN), .DI (DI_IN), .DO (DO_OUT), .DRDY (DRDY_OUT), .DWE (DWE_IN), //------------------- Shared Ports - Tile and PLL Ports -------------------- .CLKIN (CLKIN_IN), .GTPRESET (GTPRESET_IN), .GTPTEST (tied_to_ground_vec_i[3:0]), .INTDATAWIDTH (tied_to_vcc_i), .PLLLKDET (PLLLKDET_OUT), .PLLLKDETEN (tied_to_vcc_i), .PLLPOWERDOWN (tied_to_ground_i), .REFCLKOUT (REFCLKOUT_OUT), .REFCLKPWRDNB (tied_to_vcc_i), .RESETDONE0 (resetdone0_i), .RESETDONE1 (resetdone1_i), .RXENELECIDLERESETB (rxenelecidleresetb_i), .TXENPMAPHASEALIGN (tied_to_ground_i), .TXPMASETPHASE (tied_to_ground_i), //-------------- Transmit Ports - 8b10b Encoder Control Ports -------------- .TXBYPASS8B10B0 (tied_to_ground_vec_i[1:0]), .TXBYPASS8B10B1 (tied_to_ground_vec_i[1:0]), .TXCHARDISPMODE0 (tied_to_ground_vec_i[1:0]), .TXCHARDISPMODE1 (tied_to_ground_vec_i[1:0]), .TXCHARDISPVAL0 (tied_to_ground_vec_i[1:0]), .TXCHARDISPVAL1 (tied_to_ground_vec_i[1:0]), .TXCHARISK0 (TXCHARISK0_IN), .TXCHARISK1 (TXCHARISK1_IN), .TXENC8B10BUSE0 (tied_to_vcc_i), .TXENC8B10BUSE1 (tied_to_vcc_i), .TXKERR0 (), .TXKERR1 (), .TXRUNDISP0 (), .TXRUNDISP1 (), //----------- Transmit Ports - TX Buffering and Phase Alignment ------------ .TXBUFSTATUS0 (), .TXBUFSTATUS1 (), //---------------- Transmit Ports - TX Data Path interface ----------------- .TXDATA0 (txdata0_i), .TXDATA1 (txdata1_i), .TXDATAWIDTH0 (tied_to_vcc_i), .TXDATAWIDTH1 (tied_to_vcc_i), .TXOUTCLK0 (), .TXOUTCLK1 (), .TXRESET0 (TXRESET0_IN), .TXRESET1 (TXRESET1_IN), .TXUSRCLK0 (TXUSRCLK0_IN), .TXUSRCLK1 (TXUSRCLK1_IN), .TXUSRCLK20 (txusrclk20_n), .TXUSRCLK21 (txusrclk21_n), //------------- Transmit Ports - TX Driver and OOB signalling -------------- .TXBUFDIFFCTRL0 (TXDIFFCTRL0_IN), .TXBUFDIFFCTRL1 (TXDIFFCTRL1_IN), .TXDIFFCTRL0 (TXDIFFCTRL0_IN), .TXDIFFCTRL1 (TXDIFFCTRL1_IN), .TXINHIBIT0 (tied_to_ground_i), .TXINHIBIT1 (tied_to_ground_i), .TXN0 (TXN0_OUT), .TXN1 (TXN1_OUT), .TXP0 (TXP0_OUT), .TXP1 (TXP1_OUT), .TXPREEMPHASIS0 (TXPREEMPHASIS0_IN), .TXPREEMPHASIS1 (TXPREEMPHASIS1_IN), //------------------- Transmit Ports - TX PRBS Generator ------------------- .TXENPRBSTST0 (tied_to_ground_vec_i[1:0]), .TXENPRBSTST1 (tied_to_ground_vec_i[1:0]), //------------------ Transmit Ports - TX Polarity Control ------------------ .TXPOLARITY0 (tied_to_ground_i), .TXPOLARITY1 (tied_to_ground_i), //--------------- Transmit Ports - TX Ports for PCI Express ---------------- .TXDETECTRX0 (tied_to_ground_i), .TXDETECTRX1 (tied_to_ground_i), .TXELECIDLE0 (TXELECIDLE0_IN), .TXELECIDLE1 (TXELECIDLE1_IN), //------------------- Transmit Ports - TX Ports for SATA ------------------- .TXCOMSTART0 (TXCOMSTART0_IN), .TXCOMSTART1 (TXCOMSTART1_IN), .TXCOMTYPE0 (TXCOMTYPE0_IN), .TXCOMTYPE1 (TXCOMTYPE1_IN) ); endmodule
⌨️ 快捷键说明
复制代码
Ctrl + C
搜索代码
Ctrl + F
全屏模式
F11
切换主题
Ctrl + Shift + D
显示快捷键
?
增大字号
Ctrl + =
减小字号
Ctrl + -