mem_interface_top_usr_addr_fifo_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_addr_fifo_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Mon Aug 28 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module instantiates the block RAM based FIFO to store the user
//   address and the command information. Also calculates potential bank/row
//   conflicts by comparing the new address with last address issued.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_addr_fifo_0 #
  (
   parameter BANK_WIDTH    = 3,
   parameter COL_WIDTH     = 10,
   parameter CS_BITS       = 0,
   parameter ROW_WIDTH     = 14
   )
  (
   input          clk0,
   input          rst0,
   input [2:0]    app_af_cmd,
   input [30:0]   app_af_addr,
   input          app_af_wren,
   input          ctrl_af_rden,
   output [1:0]   af_conflict,
   output [2:0]   af_cmd,
   output [30:0]  af_addr,
   output         af_empty,
   output         app_af_afull
   );

  localparam ROW_RANGE_START  = COL_WIDTH;
  localparam ROW_RANGE_END    = ROW_WIDTH + ROW_RANGE_START - 1;
  localparam BANK_RANGE_START = ROW_RANGE_END + 1;
  localparam BANK_RANGE_END   = BANK_WIDTH + BANK_RANGE_START - 1;
  localparam CS_RANGE_START   = BANK_RANGE_END + 1;
  localparam CS_RANGE_END     = CS_BITS + CS_RANGE_START - 1;

  reg [30:0]                         app_af_addr_r;
  reg [2:0]                          app_af_cmd_r;
  reg                                app_af_wren_r;
  wire                               cmp_diff_bank;
  wire                               cmp_diff_row;
  wire [35:0]                        fifo_data_in;
  wire [35:0]                        fifo_data_out;
  reg [CS_RANGE_END:ROW_RANGE_START] last_addr_cmp;
  reg                                last_addr_cmp_valid;

  //***************************************************************************

  always @(posedge clk0) begin
    app_af_cmd_r  <= app_af_cmd;
    app_af_addr_r <= app_af_addr;
  end

  // store last valid value of address (cs, bank, row; don't need column)
  // also make sure very first access after reset always results in conflict
  always @(posedge clk0)
    if (rst0) begin
      last_addr_cmp_valid <= 1'b1;
      last_addr_cmp <= {(CS_RANGE_END-ROW_RANGE_START+1){1'b1}};
    end else if (app_af_wren_r) begin
      last_addr_cmp_valid <= 1'b0;
      last_addr_cmp <= app_af_addr_r[CS_RANGE_END:ROW_RANGE_START];
    end

  //***************************************************************************
  // Check for bank/row conflict between currently issued address and last
  // issued address
  //***************************************************************************

  // check to see if current address has same row as last address
  assign cmp_diff_row
    = (last_addr_cmp[ROW_RANGE_END:ROW_RANGE_START] !=
       app_af_addr_r[ROW_RANGE_END:ROW_RANGE_START]) |
      last_addr_cmp_valid;

  // check to see if current addres has same bank/cs as last address
  assign cmp_diff_bank
    = (last_addr_cmp[CS_RANGE_END:BANK_RANGE_START] !=
        app_af_addr_r[CS_RANGE_END:BANK_RANGE_START]) |
       last_addr_cmp_valid;

  //***************************************************************************
  // Format of word to/from Command/Address FIFO
  // [35] -- row conflict;
  // [34] -- bank conflict;
  // [33:31]  -- command to controller
  // [30:0]   --- address
  //***************************************************************************

  assign af_conflict = fifo_data_out[35:34];
  assign af_cmd      = fifo_data_out[33:31];
  assign af_addr     = fifo_data_out[30:0];

  assign fifo_data_in = {cmp_diff_row, cmp_diff_bank,
                         app_af_cmd_r, app_af_addr_r};

  always @(posedge clk0)
    // shouldn't need reset here if APP_AF_WREN is "well-behaved" from user
    if (rst0)
      app_af_wren_r <= 1'b0;
    else
      app_af_wren_r <= app_af_wren;

  //***************************************************************************

  FIFO36 #
    (
     .ALMOST_EMPTY_OFFSET     (13'h0007),
     .ALMOST_FULL_OFFSET      (13'h000F),
     .DATA_WIDTH              (36),
     .DO_REG                  (1),
     .EN_SYN                  ("FALSE"),
     .FIRST_WORD_FALL_THROUGH ("TRUE")
     )
    u_af
      (
       .ALMOSTEMPTY (),
       .ALMOSTFULL  (app_af_afull),
       .DO          (fifo_data_out[31:0]),
       .DOP         (fifo_data_out[35:32]),
       .EMPTY       (af_empty),
       .FULL        (),
       .RDCOUNT     (),
       .RDERR       (),
       .WRCOUNT     (),
       .WRERR       (),
       .DI          (fifo_data_in[31:0]),
       .DIP         (fifo_data_in[35:32]),
       .RDCLK       (clk0),
       .RDEN        (ctrl_af_rden),
       .RST         (rst0),
       .WRCLK       (clk0),
       .WREN        (app_af_wren_r)
       );

endmodule