mem_interface_top_usr_backend_fifo_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_backend_fifo_0.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Mon Aug 28 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module instantiates the modules containing internal FIFOs
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_backend_fifo_0 #
  (
   parameter BANK_WIDTH    = 3,
   parameter COL_WIDTH     = 10,
   parameter CS_BITS       = 0,
   parameter DQ_WIDTH      = 72,
   parameter ROW_WIDTH     = 14
   )
  (
   input                                     clk0,
   input                                     clk90,
   input                                     rst0,
   input                                     rst90,
   // Address/Command FIFO interface
   input [2:0]                               app_af_cmd,
   input [30:0]                              app_af_addr,
   input                                     app_af_wren,
   input                                     ctrl_af_rden,
   output [1:0]                              af_conflict,
   output [2:0]                              af_cmd,
   output [30:0]                             af_addr,
   output                                    af_empty,
   output                                    app_af_afull,
   // Write data FIFO interface
   input                                     app_wdf_wren,
   input [(2*DQ_WIDTH)-1:0]                  app_wdf_data,
   input [((2*DQ_WIDTH)/8)-1:0]              app_wdf_mask_data,
   input                                     wdf_rden,
   input                                     phy_init_wdf_wren,
   input [63:0]                              phy_init_wdf_data,
   output                                    app_wdf_afull,
   output [(2*DQ_WIDTH)-1:0]                 wdf_data,
   output [((2*DQ_WIDTH)/8)-1:0]             wdf_mask_data
   );

  // MASK_WIDTH = number of bytes in data bus
  localparam MASK_WIDTH = DQ_WIDTH/8;
  // determine number of FIFO72's to use based on data width
  // round up to next integer value when determining WDF_FIFO_NUM
  localparam WDF_FIFO_NUM = ((2*DQ_WIDTH)+63)/64;

  wire [WDF_FIFO_NUM-1:0]      i_wdf_afull;
  wire [DQ_WIDTH-1:0]          i_wdf_data_fall_in;
  wire [DQ_WIDTH-1:0]          i_wdf_data_fall_out;
  wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_in;
  wire [(64*WDF_FIFO_NUM)-1:0] i_wdf_data_out;
  wire [DQ_WIDTH-1:0]          i_wdf_data_rise_in;
  wire [DQ_WIDTH-1:0]          i_wdf_data_rise_out;
  wire [MASK_WIDTH-1:0]        i_wdf_mask_data_fall_in;
  wire [MASK_WIDTH-1:0]        i_wdf_mask_data_fall_out;
  wire [(8*WDF_FIFO_NUM)-1:0]  i_wdf_mask_data_in;
  wire [(8*WDF_FIFO_NUM)-1:0]  i_wdf_mask_data_out;
  wire [MASK_WIDTH-1:0]        i_wdf_mask_data_rise_in;
  wire [MASK_WIDTH-1:0]        i_wdf_mask_data_rise_out;

  //***************************************************************************

  // use almost full for first one; even though FIFO's are running in
  // asynchronous mode (CLK0 -> CLK90), there's enough padding in AF watermark
  // to account for any clock skew
  assign app_wdf_afull = i_wdf_afull[0];

  // Command/Addres FIFO
  mem_interface_top_usr_addr_fifo_0 #
    (
     .BANK_WIDTH (BANK_WIDTH),
     .COL_WIDTH  (COL_WIDTH),
     .CS_BITS    (CS_BITS),
     .ROW_WIDTH  (ROW_WIDTH)
     )
    u_usr_addr_fifo_0
    (
     .clk0         (clk0),
     .rst0         (rst0),
     .app_af_cmd   (app_af_cmd),
     .app_af_addr  (app_af_addr),
     .app_af_wren  (app_af_wren),
     .ctrl_af_rden (ctrl_af_rden),
     .af_conflict  (af_conflict),
     .af_cmd       (af_cmd),
     .af_addr      (af_addr),
     .af_empty     (af_empty),
     .app_af_afull (app_af_afull)
     );

  //***************************************************************************

  // Define intermediate buses:
  assign i_wdf_data_rise_in
    = app_wdf_data[DQ_WIDTH-1:0];
  assign i_wdf_data_fall_in
    = app_wdf_data[(2*DQ_WIDTH)-1:DQ_WIDTH];
  assign i_wdf_mask_data_rise_in
    = app_wdf_mask_data[MASK_WIDTH-1:0];
  assign i_wdf_mask_data_fall_in
    = app_wdf_mask_data[(2*MASK_WIDTH)-1:MASK_WIDTH];

  //***************************************************************************
  // Write data FIFO Input:
  // Arrange DQ's so that the rise data and fall data are interleaved.
  // the data arrives at the input of the wdf fifo as {fall,rise}.
  // It is remapped as:
  //     {...fall[15:8],rise[15:8],fall[7:0],rise[7:0]}
  // This is done to avoid having separate fifo's for rise and fall data
  // and to keep rise/fall data for the same DQ's on same FIFO
  // Data masks are interleaved in a similar manner
  // NOTE: Initialization data from PHY_INIT module does not need to be
  //  interleaved - it's already in the correct format - and the same
  //  initialization pattern from PHY_INIT is sent to all write FIFOs
  //***************************************************************************

  genvar wdf_di_i;
  generate
    for (wdf_di_i = 0; wdf_di_i < MASK_WIDTH;
         wdf_di_i = wdf_di_i + 1) begin: gen_wdf_data_in
      assign i_wdf_data_in[(16*wdf_di_i)+15:(16*wdf_di_i)]
               = {i_wdf_data_fall_in[(8*wdf_di_i)+7:(8*wdf_di_i)],
                  i_wdf_data_rise_in[(8*wdf_di_i)+7:(8*wdf_di_i)]};
      assign i_wdf_mask_data_in[(2*wdf_di_i)+1:(2*wdf_di_i)]
               = {i_wdf_mask_data_fall_in[wdf_di_i],
                  i_wdf_mask_data_rise_in[wdf_di_i]};
    end
  endgenerate

  //***************************************************************************
  // Write data FIFO Output:
  // FIFO DQ and mask outputs must be untangled and put in the standard format
  // of {fall,rise}. Same goes for mask output
  //***************************************************************************

  genvar wdf_do_i;
  generate
    for (wdf_do_i = 0; wdf_do_i < MASK_WIDTH;
         wdf_do_i = wdf_do_i + 1) begin: gen_wdf_data_out
      assign i_wdf_data_rise_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
               = i_wdf_data_out[(16*wdf_do_i)+7:(16*wdf_do_i)];
      assign i_wdf_data_fall_out[(8*wdf_do_i)+7:(8*wdf_do_i)]
               = i_wdf_data_out[(16*wdf_do_i)+15:(16*wdf_do_i)+8];
      assign i_wdf_mask_data_rise_out[wdf_do_i]
               = i_wdf_mask_data_out[2*wdf_do_i];
      assign i_wdf_mask_data_fall_out[wdf_do_i]
               = i_wdf_mask_data_out[(2*wdf_do_i)+1];
    end
  endgenerate

  assign wdf_data      = {i_wdf_data_fall_out,
                          i_wdf_data_rise_out};

  assign wdf_mask_data = {i_wdf_mask_data_fall_out,
                          i_wdf_mask_data_rise_out};

  //***************************************************************************

  genvar wdf_i;
  generate
    for (wdf_i = 0; wdf_i < WDF_FIFO_NUM; wdf_i = wdf_i + 1) begin: gen_wdf
      mem_interface_top_usr_wr_fifo u_usr_wr_fifo
        (
         .clk0              (clk0),
         .clk90             (clk90),
         .rst0              (rst0),
         .rst90             (rst90),
         .app_wdf_wren      (app_wdf_wren),
         .app_wdf_data      (i_wdf_data_in[(64*(wdf_i+1))-1:64*wdf_i]),
         .app_wdf_mask_data (i_wdf_mask_data_in[(8*(wdf_i+1))-1:8*wdf_i]),
         .phy_init_wdf_wren (phy_init_wdf_wren),
         .phy_init_wdf_data (phy_init_wdf_data),
         .wdf_rden          (wdf_rden),
         .wdf_data          (i_wdf_data_out[(64*(wdf_i+1))-1:64*wdf_i]),
         .wdf_mask_data     (i_wdf_mask_data_out[(8*(wdf_i+1))-1:8*wdf_i]),
         .wdf_afull         (i_wdf_afull[wdf_i])
         );
    end
  endgenerate

endmodule