sata_gtp.v

sata_device_model,对做硬盘控制器的朋友有帮助

    // ground and vcc signals
    wire            tied_to_ground_i;
    wire    [63:0]  tied_to_ground_vec_i;
    wire            tied_to_vcc_i;
    wire    [63:0]  tied_to_vcc_vec_i;
    
//***************************** Register Declarations *****************************

    // All TX inputs registered
     /*(* MAXDELAY="1.0" *)*/ wire    [1:0]   tile0_txcharisk0_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txcomtype0_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txelecidle0_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txcomstart0_r;
     /*(* MAXDELAY="1.0" *)*/ wire    [15:0]  tile0_txdata0_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txcomstart1_r;
     /*(* MAXDELAY="1.0" *)*/ wire    [1:0]   tile0_txcharisk1_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txcomtype1_r;
     /*(* MAXDELAY="1.0" *)*/ wire    [15:0]  tile0_txdata1_r;
     /*(* MAXDELAY="1.0" *)*/ wire            tile0_txelecidle1_r;
    

//********************************* Main Body of Code**************************

    assign tied_to_ground_i             = 1'b0;
    assign tied_to_ground_vec_i         = 64'h0000000000000000;
    assign tied_to_vcc_i                = 1'b1;
    assign tied_to_vcc_vec_i            = 64'hffffffffffffffff;
    

    //------------------------- Tile Instances  -------------------------------   



    //--------------------  Register GTP0 TX inputs for TILE0 ----------------- 

    /// synthesis attribute loc tile0_txcharisk0_r_0_i "SLICE_X58Y116"
        FD tile0_txcharisk0_r_0_i (.D(TILE0_TXCHARISK0_IN[0]),.Q(tile0_txcharisk0_r[0]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txcharisk0_r_1_i "SLICE_X58Y116"
        FD tile0_txcharisk0_r_1_i (.D(TILE0_TXCHARISK0_IN[1]),.Q(tile0_txcharisk0_r[1]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txcomtype0_r_0_i "SLICE_X58Y116"
        FD tile0_txcomtype0_r_0_i (.D(TILE0_TXCOMTYPE0_IN),.Q(tile0_txcomtype0_r),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txelecidle0_r_0_i "SLICE_X58Y116"
        FD tile0_txelecidle0_r_0_i (.D(TILE0_TXELECIDLE0_IN),.Q(tile0_txelecidle0_r),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txcomstart0_r_0_i "SLICE_X59Y116"
        FD tile0_txcomstart0_r_0_i (.D(TILE0_TXCOMSTART0_IN),.Q(tile0_txcomstart0_r),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_0_i "SLICE_X59Y116"
        FD tile0_txdata0_r_0_i (.D(TILE0_TXDATA0_IN[0]),.Q(tile0_txdata0_r[0]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_1_i "SLICE_X59Y116"
        FD tile0_txdata0_r_1_i (.D(TILE0_TXDATA0_IN[1]),.Q(tile0_txdata0_r[1]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_2_i "SLICE_X59Y116"
        FD tile0_txdata0_r_2_i (.D(TILE0_TXDATA0_IN[2]),.Q(tile0_txdata0_r[2]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_3_i "SLICE_X58Y117"
        FD tile0_txdata0_r_3_i (.D(TILE0_TXDATA0_IN[3]),.Q(tile0_txdata0_r[3]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_4_i "SLICE_X58Y117"
        FD tile0_txdata0_r_4_i (.D(TILE0_TXDATA0_IN[4]),.Q(tile0_txdata0_r[4]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_5_i "SLICE_X58Y117"
        FD tile0_txdata0_r_5_i (.D(TILE0_TXDATA0_IN[5]),.Q(tile0_txdata0_r[5]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_6_i "SLICE_X58Y117"
        FD tile0_txdata0_r_6_i (.D(TILE0_TXDATA0_IN[6]),.Q(tile0_txdata0_r[6]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_7_i "SLICE_X59Y117"
        FD tile0_txdata0_r_7_i (.D(TILE0_TXDATA0_IN[7]),.Q(tile0_txdata0_r[7]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_8_i "SLICE_X59Y117"
        FD tile0_txdata0_r_8_i (.D(TILE0_TXDATA0_IN[8]),.Q(tile0_txdata0_r[8]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_9_i "SLICE_X59Y117"
        FD tile0_txdata0_r_9_i (.D(TILE0_TXDATA0_IN[9]),.Q(tile0_txdata0_r[9]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_10_i "SLICE_X59Y117"
        FD tile0_txdata0_r_10_i (.D(TILE0_TXDATA0_IN[10]),.Q(tile0_txdata0_r[10]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_11_i "SLICE_X58Y118"
        FD tile0_txdata0_r_11_i (.D(TILE0_TXDATA0_IN[11]),.Q(tile0_txdata0_r[11]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_12_i "SLICE_X58Y118"
        FD tile0_txdata0_r_12_i (.D(TILE0_TXDATA0_IN[12]),.Q(tile0_txdata0_r[12]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_13_i "SLICE_X58Y118"
        FD tile0_txdata0_r_13_i (.D(TILE0_TXDATA0_IN[13]),.Q(tile0_txdata0_r[13]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_14_i "SLICE_X58Y118"
        FD tile0_txdata0_r_14_i (.D(TILE0_TXDATA0_IN[14]),.Q(tile0_txdata0_r[14]),.C(TILE0_TXUSRCLK20_IN));
    /// synthesis attribute loc tile0_txdata0_r_15_i "SLICE_X59Y118"
        FD tile0_txdata0_r_15_i (.D(TILE0_TXDATA0_IN[15]),.Q(tile0_txdata0_r[15]),.C(TILE0_TXUSRCLK20_IN));

    //--------------------  Register GTP1 TX inputs for TILE0 ----------------- 

    /// synthesis attribute loc tile0_txcomstart1_r_0_i "SLICE_X58Y100"
        FD tile0_txcomstart1_r_0_i (.D(TILE0_TXCOMSTART1_IN),.Q(tile0_txcomstart1_r),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txcharisk1_r_0_i "SLICE_X58Y100"
        FD tile0_txcharisk1_r_0_i (.D(TILE0_TXCHARISK1_IN[0]),.Q(tile0_txcharisk1_r[0]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txcharisk1_r_1_i "SLICE_X58Y100"
        FD tile0_txcharisk1_r_1_i (.D(TILE0_TXCHARISK1_IN[1]),.Q(tile0_txcharisk1_r[1]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txcomtype1_r_0_i "SLICE_X58Y100"
        FD tile0_txcomtype1_r_0_i (.D(TILE0_TXCOMTYPE1_IN),.Q(tile0_txcomtype1_r),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_0_i "SLICE_X59Y100"
        FD tile0_txdata1_r_0_i (.D(TILE0_TXDATA1_IN[0]),.Q(tile0_txdata1_r[0]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_1_i "SLICE_X59Y100"
        FD tile0_txdata1_r_1_i (.D(TILE0_TXDATA1_IN[1]),.Q(tile0_txdata1_r[1]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_2_i "SLICE_X59Y100"
        FD tile0_txdata1_r_2_i (.D(TILE0_TXDATA1_IN[2]),.Q(tile0_txdata1_r[2]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_3_i "SLICE_X59Y100"
        FD tile0_txdata1_r_3_i (.D(TILE0_TXDATA1_IN[3]),.Q(tile0_txdata1_r[3]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_4_i "SLICE_X58Y101"
        FD tile0_txdata1_r_4_i (.D(TILE0_TXDATA1_IN[4]),.Q(tile0_txdata1_r[4]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_5_i "SLICE_X58Y101"
        FD tile0_txdata1_r_5_i (.D(TILE0_TXDATA1_IN[5]),.Q(tile0_txdata1_r[5]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_6_i "SLICE_X58Y101"
        FD tile0_txdata1_r_6_i (.D(TILE0_TXDATA1_IN[6]),.Q(tile0_txdata1_r[6]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_7_i "SLICE_X58Y101"
        FD tile0_txdata1_r_7_i (.D(TILE0_TXDATA1_IN[7]),.Q(tile0_txdata1_r[7]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_8_i "SLICE_X59Y101"
        FD tile0_txdata1_r_8_i (.D(TILE0_TXDATA1_IN[8]),.Q(tile0_txdata1_r[8]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_9_i "SLICE_X59Y101"
        FD tile0_txdata1_r_9_i (.D(TILE0_TXDATA1_IN[9]),.Q(tile0_txdata1_r[9]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_10_i "SLICE_X59Y101"
        FD tile0_txdata1_r_10_i (.D(TILE0_TXDATA1_IN[10]),.Q(tile0_txdata1_r[10]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_11_i "SLICE_X59Y101"
        FD tile0_txdata1_r_11_i (.D(TILE0_TXDATA1_IN[11]),.Q(tile0_txdata1_r[11]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_12_i "SLICE_X58Y102"
        FD tile0_txdata1_r_12_i (.D(TILE0_TXDATA1_IN[12]),.Q(tile0_txdata1_r[12]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_13_i "SLICE_X58Y102"
        FD tile0_txdata1_r_13_i (.D(TILE0_TXDATA1_IN[13]),.Q(tile0_txdata1_r[13]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_14_i "SLICE_X58Y102"
        FD tile0_txdata1_r_14_i (.D(TILE0_TXDATA1_IN[14]),.Q(tile0_txdata1_r[14]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txdata1_r_15_i "SLICE_X58Y102"
        FD tile0_txdata1_r_15_i (.D(TILE0_TXDATA1_IN[15]),.Q(tile0_txdata1_r[15]),.C(TILE0_TXUSRCLK21_IN));
    /// synthesis attribute loc tile0_txelecidle1_r_0_i "SLICE_X59Y102"
        FD tile0_txelecidle1_r_0_i (.D(TILE0_TXELECIDLE1_IN),.Q(tile0_txelecidle1_r),.C(TILE0_TXUSRCLK21_IN));

    //_________________________________________________________________________
    //_________________________________________________________________________
    //TILE0  (Location)

    SATA_GTP_TILE #
    (
        // Simulation attributes
        .TILE_SIM_GTPRESET_SPEEDUP   (WRAPPER_SIM_GTPRESET_SPEEDUP),
        .TILE_SIM_PLL_PERDIV2        (WRAPPER_SIM_PLL_PERDIV2),

        // Channel bonding attributes
        .TILE_CHAN_BOND_MODE_0       ("OFF"),
        .TILE_CHAN_BOND_LEVEL_0      (0),
    
        .TILE_CHAN_BOND_MODE_1       ("OFF"),
        .TILE_CHAN_BOND_LEVEL_1      (0)          
    )
    tile0_sata_gtp_i
    (
        //---------------------- Loopback and Powerdown Ports ----------------------
        .LOOPBACK0_IN                   (TILE0_LOOPBACK0_IN),
        .LOOPBACK1_IN                   (TILE0_LOOPBACK1_IN),
        //--------------------- Receive Ports - 8b10b Decoder ----------------------
        .RXCHARISCOMMA0_OUT             (TILE0_RXCHARISCOMMA0_OUT),
        .RXCHARISCOMMA1_OUT             (TILE0_RXCHARISCOMMA1_OUT),
        .RXCHARISK0_OUT                 (TILE0_RXCHARISK0_OUT),
        .RXCHARISK1_OUT                 (TILE0_RXCHARISK1_OUT),
        .RXDISPERR0_OUT                 (TILE0_RXDISPERR0_OUT),
        .RXDISPERR1_OUT                 (TILE0_RXDISPERR1_OUT),
        .RXNOTINTABLE0_OUT              (TILE0_RXNOTINTABLE0_OUT),
        .RXNOTINTABLE1_OUT              (TILE0_RXNOTINTABLE1_OUT),
        //----------------- Receive Ports - Clock Correction Ports -----------------
        .RXCLKCORCNT0_OUT               (TILE0_RXCLKCORCNT0_OUT),
        .RXCLKCORCNT1_OUT               (TILE0_RXCLKCORCNT1_OUT),
        //------------- Receive Ports - Comma Detection and Alignment --------------
        .RXBYTEISALIGNED0_OUT           (TILE0_RXBYTEISALIGNED0_OUT),
        .RXBYTEISALIGNED1_OUT           (TILE0_RXBYTEISALIGNED1_OUT),
        .RXENMCOMMAALIGN0_IN            (TILE0_RXENMCOMMAALIGN0_IN),
        .RXENMCOMMAALIGN1_IN            (TILE0_RXENMCOMMAALIGN1_IN),
        .RXENPCOMMAALIGN0_IN            (TILE0_RXENPCOMMAALIGN0_IN),
        .RXENPCOMMAALIGN1_IN            (TILE0_RXENPCOMMAALIGN1_IN),
        //----------------- Receive Ports - RX Data Path interface -----------------
        .RXDATA0_OUT                    (TILE0_RXDATA0_OUT),
        .RXDATA1_OUT                    (TILE0_RXDATA1_OUT),
        .RXRESET0_IN                    (TILE0_RXRESET0_IN),
        .RXRESET1_IN                    (TILE0_RXRESET1_IN),
        .RXUSRCLK0_IN                   (TILE0_RXUSRCLK0_IN),
        .RXUSRCLK1_IN                   (TILE0_RXUSRCLK1_IN),
        .RXUSRCLK20_IN                  (TILE0_RXUSRCLK20_IN),
        .RXUSRCLK21_IN                  (TILE0_RXUSRCLK21_IN),
        //----- Receive Ports - RX Driver,OOB signalling,Coupling and Eq.,CDR ------
        .RXELECIDLE0_OUT                (TILE0_RXELECIDLE0_OUT),
        .RXELECIDLE1_OUT                (TILE0_RXELECIDLE1_OUT),
        .RXN0_IN                        (TILE0_RXN0_IN),
        .RXN1_IN                        (TILE0_RXN1_IN),
        .RXP0_IN                        (TILE0_RXP0_IN),
        .RXP1_IN                        (TILE0_RXP1_IN),
        //------ Receive Ports - RX Elastic Buffer and Phase Alignment Ports -------
        .RXSTATUS0_OUT                  (TILE0_RXSTATUS0_OUT),
        .RXSTATUS1_OUT                  (TILE0_RXSTATUS1_OUT),
        //------------- Receive Ports - RX Loss-of-sync State Machine --------------
        .RXLOSSOFSYNC0_OUT              (TILE0_RXLOSSOFSYNC0_OUT),
        .RXLOSSOFSYNC1_OUT              (TILE0_RXLOSSOFSYNC1_OUT),
        //----------- Shared Ports - Dynamic Reconfiguration Port (DRP) ------------
        .DADDR_IN                       (TILE0_DADDR_IN),
        .DCLK_IN                        (TILE0_DCLK_IN),
        .DEN_IN                         (TILE0_DEN_IN),
        .DI_IN                          (TILE0_DI_IN),
        .DO_OUT                         (TILE0_DO_OUT),
        .DRDY_OUT                       (TILE0_DRDY_OUT),
        .DWE_IN                         (TILE0_DWE_IN),
        
        //------------------- Shared Ports - Tile and PLL Ports --------------------
        .CLKIN_IN                       (TILE0_CLKIN_IN),
        .GTPRESET_IN                    (TILE0_GTPRESET_IN),
        .PLLLKDET_OUT                   (TILE0_PLLLKDET_OUT),
        .REFCLKOUT_OUT                  (TILE0_REFCLKOUT_OUT),
        .RESETDONE0_OUT                 (TILE0_RESETDONE0_OUT),
        .RESETDONE1_OUT                 (TILE0_RESETDONE1_OUT),
        //-------------- Transmit Ports - 8b10b Encoder Control Ports --------------
        .TXCHARISK0_IN                  (tile0_txcharisk0_r),
        .TXCHARISK1_IN                  (tile0_txcharisk1_r),
        //---------------- Transmit Ports - TX Data Path interface -----------------
        .TXDATA0_IN                     (tile0_txdata0_r),
        .TXDATA1_IN                     (tile0_txdata1_r),
        .TXRESET0_IN                    (TILE0_TXRESET0_IN),
        .TXRESET1_IN                    (TILE0_TXRESET1_IN),
        .TXUSRCLK0_IN                   (TILE0_TXUSRCLK0_IN),
        .TXUSRCLK1_IN                   (TILE0_TXUSRCLK1_IN),
        .TXUSRCLK20_IN                  (TILE0_TXUSRCLK20_IN),
        .TXUSRCLK21_IN                  (TILE0_TXUSRCLK21_IN),
        //------------- Transmit Ports - TX Driver and OOB signalling --------------
        .TXDIFFCTRL0_IN                 (TILE0_TXDIFFCTRL0_IN),
        .TXDIFFCTRL1_IN                 (TILE0_TXDIFFCTRL1_IN),
        .TXN0_OUT                       (TILE0_TXN0_OUT),
        .TXN1_OUT                       (TILE0_TXN1_OUT),
        .TXP0_OUT                       (TILE0_TXP0_OUT),
        .TXP1_OUT                       (TILE0_TXP1_OUT),
        .TXPREEMPHASIS0_IN              (TILE0_TXPREEMPHASIS0_IN),
        .TXPREEMPHASIS1_IN              (TILE0_TXPREEMPHASIS1_IN),
        //--------------- Transmit Ports - TX Ports for PCI Express ----------------
        .TXELECIDLE0_IN                 (tile0_txelecidle0_r),
        .TXELECIDLE1_IN                 (tile0_txelecidle1_r),
        //------------------- Transmit Ports - TX Ports for SATA -------------------
        .TXCOMSTART0_IN                 (tile0_txcomstart0_r),
        .TXCOMSTART1_IN                 (tile0_txcomstart1_r),
        .TXCOMTYPE0_IN                  (tile0_txcomtype0_r),
        .TXCOMTYPE1_IN                  (tile0_txcomtype1_r)

    );

    
     
endmodule