ddr2_sodimm.v

sata_device_model,对做硬盘控制器的朋友有帮助

/****************************************************************************************
*
*    File Name:  ddr2_sodimm.v
*      Version:  5.00
*        Model:  BUS Functional
*
* Dependencies:  ddr2.v, ddr2_parameters.vh
*
*****************************************************************************************/

`timescale 1ps / 1ps
//can handle 512M
module ddr2_sodimm(
input  wire        clk0,
input  wire        clk0_n,
input  wire        clk1,
input  wire        clk1_n,
input  wire        cke,
input  wire        cs_n,
input  wire        ras_n,
input  wire        cas_n,
input  wire        we_n,
inout  wire  [7:0] dm_rdqs,
input  wire        s_n,
input  wire  [2:0] ba,
input  wire [12:0] a,
inout  wire [63:0] dq,
inout  wire  [7:0] dqs,
inout  wire  [7:0] dqs_n,
output wire        rdqs_n,
input  wire        odt
);




`include "ddr2_parameters.vh"


ddr2 sdramddr2_1 (
   .ck      (clk0), 
   .ck_n    (clk0_n), 
   .cke     (cke), 
   .cs_n    (s_n), 
   .ras_n   (ras_n), 
   .cas_n   (cas_n), 
   .we_n    (we_n), 
   .dm_rdqs (dm_rdqs[1:0]), 
   .ba      (ba[1:0]), 
   .addr    (a), 
   .dq      (dq[15:0]), 
   .dqs     ({dqs[1],dqs[0]}),
   .dqs_n   ({dqs_n[1],dqs_n[0]}),
   .rdqs_n  (),
   .odt     (odt)
   );

ddr2 sdramddr2_2 (
   .ck      (clk0), 
   .ck_n    (clk0_n), 
   .cke     (cke), 
   .cs_n    (s_n), 
   .ras_n   (ras_n), 
   .cas_n   (cas_n), 
   .we_n    (we_n), 
   .dm_rdqs (dm_rdqs[3:2]), 
   .ba      (ba[1:0]), 
   .addr    (a), 
   .dq      (dq[31:16]), 
   .dqs     ({dqs[3],dqs[2]}),
   .dqs_n   ({dqs_n[3],dqs_n[2]}),
   .rdqs_n  (),
   .odt     (odt)
   );

ddr2 sdramddr2_3 (
   .ck      (clk1), 
   .ck_n    (clk1_n), 
   .cke     (cke), 
   .cs_n    (s_n), 
   .ras_n   (ras_n), 
   .cas_n   (cas_n), 
   .we_n    (we_n), 
   .dm_rdqs (dm_rdqs[5:4]), 
   .ba      (ba[1:0]), 
   .addr    (a), 
   .dq      (dq[47:32]), 
   .dqs     ({dqs[5],dqs[4]}),
   .dqs_n   ({dqs_n[5],dqs_n[4]}),
   .rdqs_n  (),
   .odt     (odt)
   );

ddr2 sdramddr2_4 (
   .ck      (clk1), 
   .ck_n    (clk1_n), 
   .cke     (cke), 
   .cs_n    (s_n), 
   .ras_n   (ras_n), 
   .cas_n   (cas_n), 
   .we_n    (we_n), 
   .dm_rdqs (dm_rdqs[7:6]), 
   .ba      (ba[1:0]), 
   .addr    (a), 
   .dq      (dq[63:48]), 
   .dqs     ({dqs[6],dqs[7]}),
   .dqs_n   ({dqs_n[6],dqs_n[7]}),
   .rdqs_n  (),
   .odt     (odt)
   );

    
endmodule