mem_interface_top_usr_wr_fifo_0.v

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//*****************************************************************************
// Copyright (c) 2006 Xilinx, Inc.
// This design is confidential and proprietary of Xilinx, Inc.
// All Rights Reserved
//*****************************************************************************
//   ____  ____
//  /   /\/   /
// /___/  \  /    Vendor: Xilinx
// \   \   \/     Version: $Name: i+IP+125372 $
//  \   \         Application: MIG
//  /   /         Filename: mem_interface_top_usr_wr_fifo.v
// /___/   /\     Date Last Modified: $Date: 2007/04/18 13:49:32 $
// \   \  /  \    Date Created: Mon Aug 28 2006
//  \___\/\___\
//
//Device: Virtex-5
//Design Name: DDR2
//Purpose:
//   This module instantiates the block RAM based FIFO to store the user
//   interface data into it and read after a specified amount in already
//   written. The reading starts when the almost full signal is generated
//   whose offset is programmable.
//Reference:
//Revision History:
//*****************************************************************************

`timescale 1ns/1ps

module mem_interface_top_usr_wr_fifo
  (
   input          clk0,
   input          clk90,
   input          rst0,
   input          rst90,
   input          app_wdf_wren,
   input [63:0]   app_wdf_data,
   input [7:0]    app_wdf_mask_data,
   input          wdf_rden,
   input          phy_init_wdf_wren,
   input [63:0]   phy_init_wdf_data,
   output [63:0]  wdf_data,
   output [7:0]   wdf_mask_data,
   output         wdf_afull
   );

  wire [63:0]     i_wdf_data_in;
  wire [7:0]      i_wdf_mask_data_in;
  wire            i_wdf_wren;

  //***************************************************************************

  // requires that User I/F drive WREN, DATA, and MASK with zeroes until init
  // is finished.
  assign i_wdf_wren = app_wdf_wren | phy_init_wdf_wren;
  assign i_wdf_data_in = app_wdf_data | phy_init_wdf_data;
  assign i_wdf_mask_data_in = app_wdf_mask_data;

  FIFO36_72  #
    (
     .ALMOST_EMPTY_OFFSET     (9'h007),
     .ALMOST_FULL_OFFSET      (9'h00F),
     .DO_REG                  (1),          // extra CC output delay
     .EN_ECC_WRITE            ("FALSE"),
     .EN_ECC_READ             ("FALSE"),
     .EN_SYN                  ("FALSE"),
     .FIRST_WORD_FALL_THROUGH ("FALSE")
     )
    u_wdf
      (
       .ALMOSTEMPTY (),
       .ALMOSTFULL  (wdf_afull),
       .DBITERR     (),
       .DO          (wdf_data),
       .DOP         (wdf_mask_data),
       .ECCPARITY   (),
       .EMPTY       (),
       .FULL        (),
       .RDCOUNT     (),
       .RDERR       (),
       .SBITERR     (),
       .WRCOUNT     (),
       .WRERR       (),
       .DI          (i_wdf_data_in),
       .DIP         (i_wdf_mask_data_in),
       .RDCLK       (clk90),
       .RDEN        (wdf_rden),
       .RST         (rst90),          // or can use rst0
       .WRCLK       (clk0),
       .WREN        (i_wdf_wren)
       );

endmodule